From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 24 Jan 2014 14:05:24 +0000 (+0100)
Subject: Fixed handling of unsized constants in verilog frontend
X-Git-Tag: yosys-0.2.0~150
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b47d907d36842e0971dd038b5fb6093ca303a8a;p=yosys.git

Fixed handling of unsized constants in verilog frontend
---

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index e38ff2047..c95ce5dc4 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -99,7 +99,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 
 	int bits_per_digit = my_ilog2(base-1);
 	if (len_in_bits < 0)
-		len_in_bits = digits.size() * bits_per_digit;
+		len_in_bits = std::max<int>(digits.size() * bits_per_digit, 32);
 
 	data.clear();
 	data.resize(len_in_bits);
@@ -157,7 +157,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
 	if (*endptr == 0)
 		return AstNode::mkconst_int(intval, true);
 	
-	// variable length constant
+	// unsized constant
 	if (str == endptr)
 		intval = -1;