From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Oct 2013 11:27:35 +0000 (+0100)
Subject: Added DFFSR cell to techlibs/cmos/cmos_cells.lib
X-Git-Tag: yosys-0.2.0~424
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b4a64ac6adbd6;p=yosys.git

Added DFFSR cell to techlibs/cmos/cmos_cells.lib
---

diff --git a/techlibs/cmos/cmos_cells.lib b/techlibs/cmos/cmos_cells.lib
index 1d7b8279c..164256c01 100644
--- a/techlibs/cmos/cmos_cells.lib
+++ b/techlibs/cmos/cmos_cells.lib
@@ -29,4 +29,18 @@ library(demo) {
     pin(Q) { direction: output;
               function: "IQ"; }
   }
+  cell(DFFSR) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D;
+                      preset: S;
+                       clear: R; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+    pin(S) { direction: input; }
+    pin(R) { direction: input; }
+  }
 }
diff --git a/techlibs/cmos/cmos_cells.v b/techlibs/cmos/cmos_cells.v
index 802f58718..da75270cb 100644
--- a/techlibs/cmos/cmos_cells.v
+++ b/techlibs/cmos/cmos_cells.v
@@ -21,3 +21,15 @@ always @(posedge C)
 	Q <= D;
 endmodule
 
+module DFFSR(C, D, Q, S, R);
+input C, D, S, R;
+output reg Q;
+always @(posedge C, posedge S, posedge R)
+	if (S)
+		Q <= 1'b1;
+	else if (R)
+		Q <= 1'b0;
+	else
+		Q <= D;
+endmodule
+