From: lkcl Date: Tue, 25 Apr 2023 15:04:03 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b6059d800a5717b791ae0ff95a5be72785da3d5;p=libreriscv.git --- diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 4b4e08de4..53b0965cb 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -16,25 +16,8 @@ See: Please see [[svp64/appendix]] regarding CR bit ordering and for the definition of `CR{n}` ----------- - -\newpage{} +# Instructions -# Instruction form and pseudocode - -**DRAFT** Instruction format (use of MAJOR 19 not approved by -OPF ISA WG): - -|0-5|6-10 |11|12-15|16-18|19-20|21-25 |26-30 |31|name | -|---|---- |--|-----|-----|-----|----- |----- |--|---- | -|19 |RT | |fmsk |BFA | |XO[0:4]|XO[5:9]|/ | | -|19 | | | | | |1 //// |00011 | |rsvd | -|19 |RT |M |fmsk |BFA | 0 0 |0 fmap |00011 |Rc|crrweird | -|19 |RT |M |fmsk |BFA | 0 1 |0 fmap |00011 |Rc|mfcrweird | -|19 |RA |M |fmsk |BF | 1 0 |0 fmap |00011 |0 |mtcrrweird | -|19 |RA |M |fmsk |BF | 1 0 |0 fmap |00011 |1 |mtcrweird | -|19 |BT |M |fmsk |BFA | 1 1 |0 fmap |00011 |0 |crweirder | -|19 |BF //|M |fmsk |BFA | 1 1 |0 fmap |00011 |1 |mcrfm | ## crrweird @@ -46,8 +29,8 @@ CW2-Form ``` -* crrweird RT,BFA,M,fmsk,fmap -* crrweird. RT,BFA,M,fmsk,fmap +* crrweird RT,BFA,M,fmsk,fmap (Rc=0) +* crrweird. RT,BFA,M,fmsk,fmap (Rc=1) ``` creg = CR{BFA} @@ -78,16 +61,19 @@ Special registers altered: ## mfcrrweird +CW2-Form + ``` |0 |6 |9 |11|12 |16 |19 |22 |26 |31| - | PO | RA |M |fmsk |BF |XO |fmap | XO | - | PO | BT |M |fmsk |BF |XO |fmap | XO | - | PO | BF | |M |fmsk |BF |XO |fmap | XO | + | PO | RT |M |fmsk |BFA |XO |fmap | XO |Rc| + ``` +* mfcrrweird RT,BFA,fmsk,fmap (Rc=0) +* mfcrrweird. RT,BFA,fmsk,fmap (Rc=1) ``` - mfcrrweird: RT,BFA,fmsk,fmap + creg = CR{BFA} n0 = fmsk[0] & (fmap[0] == creg[0])