From: Sebastien Bourdeauducq Date: Mon, 30 Apr 2012 21:38:17 +0000 (-0500) Subject: sim: pass extra keyword arguments to Verilog converter X-Git-Tag: 24jan2021_ls180~2099^2~950 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b62e573aea43087e6f98ae762d32939c4766583;p=litex.git sim: pass extra keyword arguments to Verilog converter --- diff --git a/doc/index.rst b/doc/index.rst index b7a03d67..8db436f2 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -474,6 +474,7 @@ The constructor of the ``Simulator`` object takes the following parameters: #. A simulator runner object (see :ref:`simrunner`). #. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself. #. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket"). +#. Additional keyword arguments (if any) are passed to the Verilog conversion function. Running the simulation ====================== diff --git a/migen/sim/generic.py b/migen/sim/generic.py index b0d369d9..323f62ff 100644 --- a/migen/sim/generic.py +++ b/migen/sim/generic.py @@ -68,7 +68,7 @@ end return r class Simulator: - def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket"): + def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket", **vopts): self.fragment = fragment if top_level is None: self.top_level = TopLevel() @@ -85,7 +85,8 @@ class Simulator: name=self.top_level.dut_type, clk_signal=clk_signal, rst_signal=rst_signal, - return_ns=True) + return_ns=True, + **vopts) self.cycle_counter = -1 self.interrupt = False