From: Andrey Belevantsev <abel@ispras.ru>
Date: Tue, 22 Mar 2011 12:33:53 +0000 (+0300)
Subject: re PR rtl-optimization/48143 (ICE: in reset_sched_cycles_in_current_ebb, at sel-sched... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b7e851b85afb78125a8cce3f5f0bf332124541f;p=gcc.git

re PR rtl-optimization/48143 (ICE: in reset_sched_cycles_in_current_ebb, at sel-sched.c:7114 with custom flags)

        PR rtl-optimization/48143
        * config/i386/sse.md (*sse2_cvtpd2dq): Add athlon_decode attribute.
        (*sse2_cvttpd2dq, sse2_cvtss2sd, *sse2_cvtpd2ps,
        sse2_cvtps2pd): Likewise.

From-SVN: r171286
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7aac8837ea0..6d318e05952 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2011-03-22  Andrey Belevantsev  <abel@ispras.ru>
+
+	PR rtl-optimization/48143
+	* config/i386/sse.md (*sse2_cvtpd2dq): Add athlon_decode attribute.
+	(*sse2_cvttpd2dq, sse2_cvtss2sd, *sse2_cvtpd2ps,
+	sse2_cvtps2pd): Likewise.
+
 2011-03-22  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
 	* recog.c (canonicalize_change_group): Use validate_unshare_change.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 62004198548..70a0b344bdf 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2715,6 +2715,7 @@
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")
    (set_attr "amdfam10_decode" "double")
+   (set_attr "athlon_decode" "vector")
    (set_attr "bdver1_decode" "double")])
 
 (define_insn "avx_cvttpd2dq256"
@@ -2746,6 +2747,7 @@
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")
    (set_attr "amdfam10_decode" "double")
+   (set_attr "athlon_decode" "vector")
    (set_attr "bdver1_decode" "double")])
 
 (define_insn "*avx_cvtsd2ss"
@@ -2806,6 +2808,7 @@
   "cvtss2sd\t{%2, %0|%0, %2}"
   [(set_attr "type" "ssecvt")
    (set_attr "amdfam10_decode" "vector,double")
+   (set_attr "athlon_decode" "direct,direct")
    (set_attr "bdver1_decode" "direct,direct")
    (set_attr "mode" "DF")])
 
@@ -2842,6 +2845,7 @@
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "V4SF")
    (set_attr "amdfam10_decode" "double")
+   (set_attr "athlon_decode" "vector")
    (set_attr "bdver1_decode" "double")])
 
 (define_insn "avx_cvtps2pd256"
@@ -2879,6 +2883,7 @@
    (set_attr "mode" "V2DF")
    (set_attr "prefix_data16" "0")
    (set_attr "amdfam10_decode" "direct")
+   (set_attr "athlon_decode" "double")
    (set_attr "bdver1_decode" "double")])
 
 (define_expand "vec_unpacks_hi_v4sf"