From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Fri, 27 Oct 2023 10:22:49 +0000 (+0100)
Subject: added english language description for lbzsux instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b9913741ff36766f93279495f0a9a1b3d8403b2;p=openpower-isa.git

added english language description for lbzsux instruction
---

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 481547c9..7a4fe660 100644
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -42,6 +42,7 @@ Description:
 
     Let the effective address (EA) be the sum of the contents of
     register RB shifted by (SH+1), and (RA|0).
+
     The byte in storage addressed by EA is loaded into
     RT[56:63]. RT[0:55] are set to 0.
 
@@ -62,6 +63,18 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and (RA).
+
+    The byte in storage addressed by EA is
+    loaded into RT[56:63] . RT[0:55] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None