From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Jun 2020 18:21:20 +0000 (+0100)
Subject: move debug statements to check function
X-Git-Tag: div_pipeline~356
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0babe500e0ff03c6831e2a64691725e8dc7ddb3d;p=soc.git

move debug statements to check function
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 0afe5556..7e13dfe8 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -33,6 +33,7 @@ from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
 
 def setup_regs(core, test):
 
+
     # set up INT regfile, "direct" write (bypass rd/write ports)
     intregs = core.regs.int
     for i in range(32):
@@ -69,6 +70,16 @@ def setup_regs(core, test):
         yield xregs.regs[xregs.OV].reg.eq(0)
         yield xregs.regs[xregs.CA].reg.eq(0)
 
+    # XER
+    so = yield xregs.regs[xregs.SO].reg
+    ov = yield xregs.regs[xregs.OV].reg
+    ca = yield xregs.regs[xregs.CA].reg
+    oe = yield pdecode2.e.oe.oe
+    oe_ok = yield pdecode2.e.oe.oe_ok
+
+    print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
+    print ("oe:", oe, oe_ok)
+
 
 def check_regs(dut, sim, core, test, code):
     # int regs
@@ -198,17 +209,6 @@ class TestRunner(FHDLTestCase):
                     #fuval = self.funit.value
                     #self.assertEqual(fn_unit & fuval, fuval)
 
-                    # XER
-                    xregs = core.regs.xer
-                    so = yield xregs.regs[xregs.SO].reg
-                    ov = yield xregs.regs[xregs.OV].reg
-                    ca = yield xregs.regs[xregs.CA].reg
-                    oe = yield pdecode2.e.oe.oe
-                    oe_ok = yield pdecode2.e.oe.oe_ok
-
-                    print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
-                    print ("oe:", oe, oe_ok)
-
                     # set operand and get inputs
                     yield from set_issue(core, pdecode2, sim)
                     yield Settle()