From: Jacob Lifshay Date: Wed, 11 May 2022 08:24:04 +0000 (-0700) Subject: fix some borked imports X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bbeb482f03889c64d25a5da3c7d407f56ea2456;p=ieee754fpu.git fix some borked imports --- diff --git a/src/ieee754/add/test_inputgroup.py b/src/ieee754/add/test_inputgroup.py index 96de216f..b4870439 100644 --- a/src/ieee754/add/test_inputgroup.py +++ b/src/ieee754/add/test_inputgroup.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from inputgroup import InputGroup +from ieee754.add.inputgroup import InputGroup def testbench(dut): diff --git a/src/ieee754/add/test_state_add.py b/src/ieee754/add/test_state_add.py index e38e3e66..0d950092 100644 --- a/src/ieee754/add/test_state_add.py +++ b/src/ieee754/add/test_state_add.py @@ -5,12 +5,13 @@ from operator import add from nmigen import Module, Signal from nmigen.compat.sim import run_simulation -from fadd_state import FPADD +from ieee754.fpadd.fadd_state import FPADD -from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan, - is_inf, is_pos_inf, is_neg_inf, - match, get_case, check_case, run_fpunit, - run_edge_cases, run_corner_cases) +from ieee754.fpcommon.test.unit_test_single import ( + get_mantissa, get_exponent, get_sign, is_nan, + is_inf, is_pos_inf, is_neg_inf, + match, get_case, check_case, run_fpunit, + run_edge_cases, run_corner_cases) def testbench(dut): yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0xFFC00000) diff --git a/src/ieee754/add/test_syncops.py b/src/ieee754/add/test_syncops.py index 484597ca..2c9bbaa8 100644 --- a/src/ieee754/add/test_syncops.py +++ b/src/ieee754/add/test_syncops.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal from nmigen.compat.sim import run_simulation from nmigen.cli import verilog -from inputgroup import FPGetSyncOpsMod +from ieee754.add.inputgroup import FPGetSyncOpsMod def testbench(dut): diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py index db8c7a17..05c667e7 100644 --- a/src/ieee754/cordic/test/test_fp_pipe.py +++ b/src/ieee754/cordic/test/test_fp_pipe.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Passive -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from sfpy import Float32 diff --git a/src/ieee754/cordic/test/test_fpsin_cos.py b/src/ieee754/cordic/test/test_fpsin_cos.py index a98db72d..993e202a 100644 --- a/src/ieee754/cordic/test/test_fpsin_cos.py +++ b/src/ieee754/cordic/test/test_fpsin_cos.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from ieee754.cordic.fpsin_cos import CORDIC from ieee754.fpcommon.fpbase import FPNumBaseRecord diff --git a/src/ieee754/cordic/test/test_sincos.py b/src/ieee754/cordic/test/test_sincos.py index f565b1ce..1fb27f7d 100644 --- a/src/ieee754/cordic/test/test_sincos.py +++ b/src/ieee754/cordic/test/test_sincos.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from ieee754.cordic.sin_cos import CORDIC from python_sin_cos import run_cordic diff --git a/src/ieee754/fpcmp/formal/proof_fpcmp_mod.py b/src/ieee754/fpcmp/formal/proof_fpcmp_mod.py index 4f3d273e..efc2c7b7 100644 --- a/src/ieee754/fpcmp/formal/proof_fpcmp_mod.py +++ b/src/ieee754/fpcmp/formal/proof_fpcmp_mod.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux from nmigen.asserts import Assert, AnyConst -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord from ieee754.fpcmp.fpcmp import FPCMPPipeMod diff --git a/src/ieee754/fpmax/formal/proof_fmax_mod.py b/src/ieee754/fpmax/formal/proof_fmax_mod.py index 70081196..2ca7d407 100644 --- a/src/ieee754/fpmax/formal/proof_fmax_mod.py +++ b/src/ieee754/fpmax/formal/proof_fmax_mod.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux from nmigen.asserts import Assert, AnyConst -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord from ieee754.fpmax.fpmax import FPMAXPipeMod diff --git a/src/ieee754/fpmul/fmul.py b/src/ieee754/fpmul/fmul.py index d775671c..dd525b0e 100644 --- a/src/ieee754/fpmul/fmul.py +++ b/src/ieee754/fpmul/fmul.py @@ -3,7 +3,7 @@ from nmigen.cli import main, verilog from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState) -from ieee754.fpcommon.getop import FPGetOp +#from ieee754.fpcommon.getop import FPGetOp from nmutil.nmoperator import eq diff --git a/src/ieee754/fpmul/test/test_mul64.py b/src/ieee754/fpmul/test/test_mul64.py index 5f8eb305..93d62406 100644 --- a/src/ieee754/fpmul/test/test_mul64.py +++ b/src/ieee754/fpmul/test/test_mul64.py @@ -2,18 +2,18 @@ from nmigen import Module, Signal from nmigen.compat.sim import run_simulation from operator import mul -from fmul import FPMUL +from ieee754.fpmul.fmul import FPMUL import sys import atexit from random import randint from random import seed -from unit_test_double import (get_mantissa, get_exponent, get_sign, is_nan, - is_inf, is_pos_inf, is_neg_inf, - match, get_case, check_case, run_fpunit, - run_edge_cases, run_corner_cases) - +from ieee754.fpcommon.test.unit_test_double import ( + get_mantissa, get_exponent, get_sign, is_nan, + is_inf, is_pos_inf, is_neg_inf, + match, get_case, check_case, run_fpunit, + run_edge_cases, run_corner_cases) def testbench(dut): yield from check_case(dut, 0, 0, 0) diff --git a/src/ieee754/fsgnj/formal/proof_fsgnj_mod.py b/src/ieee754/fsgnj/formal/proof_fsgnj_mod.py index b960a85c..2a744bdf 100644 --- a/src/ieee754/fsgnj/formal/proof_fsgnj_mod.py +++ b/src/ieee754/fsgnj/formal/proof_fsgnj_mod.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable from nmigen.asserts import Assert, Assume -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord from ieee754.fsgnj.fsgnj import FSGNJPipeMod diff --git a/src/ieee754/part_cmp/experiments/formal/proof_eq.py b/src/ieee754/part_cmp/experiments/formal/proof_eq.py index 80fd7f1d..e692956e 100644 --- a/src/ieee754/part_cmp/experiments/formal/proof_eq.py +++ b/src/ieee754/part_cmp/experiments/formal/proof_eq.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux from nmigen.asserts import Assert, AnyConst -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from ieee754.part_cmp.experiments.eq_combiner import EQCombiner diff --git a/src/ieee754/part_cmp/experiments/formal/proof_equal.py b/src/ieee754/part_cmp/experiments/formal/proof_equal.py index 441a4c7b..e21b1745 100644 --- a/src/ieee754/part_cmp/experiments/formal/proof_equal.py +++ b/src/ieee754/part_cmp/experiments/formal/proof_equal.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux from nmigen.asserts import Assert, AnyConst, Assume -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from ieee754.part_mul_add.partpoints import PartitionPoints diff --git a/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py b/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py index 13c42343..4ad359d5 100644 --- a/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py +++ b/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux, Cat from nmigen.asserts import Assert, AnyConst, Assume -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from ieee754.part_mul_add.partpoints import PartitionPoints diff --git a/src/ieee754/part_cmp/formal/proof_gt.py b/src/ieee754/part_cmp/formal/proof_gt.py index a64eca0f..366f2f87 100644 --- a/src/ieee754/part_cmp/formal/proof_gt.py +++ b/src/ieee754/part_cmp/formal/proof_gt.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux from nmigen.asserts import Assert, AnyConst, Assume -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from ieee754.part_cmp.gt_combiner import GTCombiner diff --git a/src/ieee754/part_shift/formal/proof_shift_dynamic.py b/src/ieee754/part_shift/formal/proof_shift_dynamic.py index 9c160762..f5bdc256 100644 --- a/src/ieee754/part_shift/formal/proof_shift_dynamic.py +++ b/src/ieee754/part_shift/formal/proof_shift_dynamic.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux, Cat from nmigen.asserts import Assert, AnyConst -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from ieee754.part_mul_add.partpoints import PartitionPoints diff --git a/src/ieee754/part_shift/formal/proof_shift_scalar.py b/src/ieee754/part_shift/formal/proof_shift_scalar.py index 7c0d7593..5f0666f8 100644 --- a/src/ieee754/part_shift/formal/proof_shift_scalar.py +++ b/src/ieee754/part_shift/formal/proof_shift_scalar.py @@ -3,7 +3,7 @@ from nmigen import Module, Signal, Elaboratable, Mux, Cat from nmigen.asserts import Assert, AnyConst, Assume -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from ieee754.part_mul_add.partpoints import PartitionPoints diff --git a/src/ieee754/part_shift/test/test_shift_dynamic.py b/src/ieee754/part_shift/test/test_shift_dynamic.py index 86db976c..fac0ff1a 100644 --- a/src/ieee754/part_shift/test/test_shift_dynamic.py +++ b/src/ieee754/part_shift/test/test_shift_dynamic.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from ieee754.part_mul_add.partpoints import PartitionPoints from ieee754.part_shift.part_shift_dynamic import \ diff --git a/src/ieee754/part_shift/test/test_shift_scalar.py b/src/ieee754/part_shift/test/test_shift_scalar.py index 579e1dc6..6d2640a8 100644 --- a/src/ieee754/part_shift/test/test_shift_scalar.py +++ b/src/ieee754/part_shift/test/test_shift_scalar.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase +from nmutil.formaltest import FHDLTestCase from ieee754.part_mul_add.partpoints import PartitionPoints from ieee754.part_shift.part_shift_scalar import \