From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 22 May 2014 14:11:32 +0000 (+0200)
Subject: fix uart selection when opening wishbone
X-Git-Tag: 24jan2021_ls180~2575^2~76
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bc1cd6f777b7af91fda966513fcb64d7465437a;p=litex.git

fix uart selection when opening wishbone
---

diff --git a/miscope/host/uart2wishbone.py b/miscope/host/uart2wishbone.py
index ca4e5874..df79a1a1 100644
--- a/miscope/host/uart2wishbone.py
+++ b/miscope/host/uart2wishbone.py
@@ -23,13 +23,13 @@ class Uart2Wishbone:
 		self.uart.open()
 		self.uart.flushInput()
 		try:
-			wb.regs.uart2wb_sel.write(1)
+			self.regs.uart2wb_sel.write(1)
 		except:
 			pass
 		
 	def close(self):
 		try:
-			wb.regs.uart2wb_sel.write(0)
+			self.regs.uart2wb_sel.write(0)
 		except:
 			pass
 		self.uart.close()
diff --git a/miscope/host/vcd.py b/miscope/host/vcd.py
index 4b2bad8a..0259e609 100644
--- a/miscope/host/vcd.py
+++ b/miscope/host/vcd.py
@@ -1,7 +1,17 @@
 import sys
 import datetime
 
-from miscope.std.misc import *
+def dec2bin(d, nb=0):
+	if d=="x":
+		return "x"*nb
+	elif d==0:
+		b="0"
+	else:
+		b=""
+		while d!=0:
+			b="01"[d&1]+b
+			d=d>>1
+	return b.zfill(nb)
 
 def get_bits(values, width, low, high=None):
 	r = []