From: Michael Nolan <mtnolan2640@gmail.com>
Date: Tue, 28 Apr 2020 17:55:53 +0000 (-0400)
Subject: Add cordic stages to fp cordic pipeline
X-Git-Tag: ls180-24jan2020~75
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bc2151db647aaeb55aa7d62f0dfe89bc8ea9080;p=ieee754fpu.git

Add cordic stages to fp cordic pipeline
---

diff --git a/src/ieee754/cordic/fp_pipeline.py b/src/ieee754/cordic/fp_pipeline.py
index 9ceaaea4..2b0b8287 100644
--- a/src/ieee754/cordic/fp_pipeline.py
+++ b/src/ieee754/cordic/fp_pipeline.py
@@ -4,6 +4,8 @@ from nmutil.pipemodbase import PipeModBaseChain
 from ieee754.fpcommon.denorm import FPAddDeNormMod
 from ieee754.cordic.fp_pipe_init_stages import (FPCordicInitStage,
                                                 FPCordicConvertFixed)
+from ieee754.cordic.sin_cos_pipe_stage import (CordicStage,
+                                               CordicInitialStage)
 
 
 class CordicPipeChain(PipeModBaseChain):
@@ -25,7 +27,18 @@ class FPCordicBasePipe(ControlBase):
                                        FPAddDeNormMod(self.pspec, False),
                                        FPCordicConvertFixed(self.pspec)])
 
-        self._eqs = self.connect([self.denorm])
+        self.cordicstages = []
+
+        initstage = CordicInitialStage(pspec)
+        stages = []
+        for i in range(pspec.iterations):
+            stages.append(CordicStage(pspec, i))
+        chunks = self.chunkify(initstage, stages)
+        for chunk in chunks:
+            chain = CordicPipeChain(pspec, chunk)
+            self.cordicstages.append(chain)
+
+        self._eqs = self.connect([self.denorm] + self.cordicstages)
 
     def chunkify(self, initstage, stages):
         chunks = []
@@ -39,5 +52,8 @@ class FPCordicBasePipe(ControlBase):
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
         m.submodules.denorm = self.denorm
+        for i, stage in enumerate(self.cordicstages):
+            setattr(m.submodules, "cordic%d" % i,
+                    stage)
         m.d.comb += self._eqs
         return m
diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index 1b2ead12..295c3c4f 100644
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -47,7 +47,7 @@ class SinCosTestCase(FHDLTestCase):
 
         sim.add_sync_process(writer_process)
         with sim.write_vcd("fp_pipeline.vcd", "fp_pipeline.gtkw", traces=[
-                z, dut.n.data_o.z0]):
+                z]):
             sim.run()
 
     def test_rand(self):