From: Luke Kenneth Casson Leighton Date: Fri, 9 Nov 2018 03:02:14 +0000 (+0000) Subject: add extra mulh sv elwidth tests X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bc79da9c4a1505c7e3ba60d320f1c644b42494d;p=riscv-tests.git add extra mulh sv elwidth tests --- diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index 18de70d..f725de9 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -77,11 +77,11 @@ #define TEST_SV_IMMW( reg, imm ) \ li t6, MASK_XLEN(imm) ; \ - bne reg, t6, fail + bne reg, t6, fail; #define TEST_SV_IMM( reg, imm ) \ li t6, ((imm) & 0xffffffffffffffff); \ - bne reg, t6, fail + bne reg, t6, fail; #define TEST_SV_FD( flags, freg, from, offs ) \ fsflags x2, x0; \ @@ -90,7 +90,7 @@ la x1, from; \ ld x1, offs(x1); \ fmv.x.d x2, freg; \ - bne x2, x1, fail + bne x2, x1, fail; #define TEST_SV_FW( flags, freg, from, offs ) \ fsflags x2, x0; \ @@ -99,7 +99,7 @@ la x1, from; \ lw x1, offs(x1); \ fmv.x.s x2, freg; \ - bne x2, x1, fail + bne x2, x1, fail; #define SV_W_DFLT 0 #define SV_W_8BIT 1 diff --git a/isa/rv32um/sv_mulhu_elwidth.S b/isa/rv32um/sv_mulhu_elwidth.S index 40395d2..294b056 100644 --- a/isa/rv32um/sv_mulhu_elwidth.S +++ b/isa/rv32um/sv_mulhu_elwidth.S @@ -54,11 +54,15 @@ RVTEST_CODE_BEGIN # Start of test code. 0x7fffc000, 0x0001fefe, 0xfe010000 ) SV_ELWIDTH_TEST( 3, 2, 2, 0, 1, 1, 1, 0x00000000, 0x00007fff, 0x0000a9a8 ) -/* SV_ELWIDTH_TEST( 3, 2, 2, 2, 1, 1, 1, 0x7fff0000, 0xa5a5a9a8, 0xa5a5a5a5 ) - SV_ELWIDTH_TEST( 3, 1, 1, 3, 1, 1, 1, - 0x0000001100000009, 0xa5a5a5a500000019, 0xa5a5a5a5a5a5a5a5 ) + SV_ELWIDTH_TEST( 3, 2, 2, 1, 1, 1, 1, + 0xa5a8ff00, 0xa5a5a5a5, 0xa5a5a5a5 ) + SV_ELWIDTH_TEST( 3, 3, 3, 1, 1, 1, 1, + 0xa500fe00, 0xa5a5a5a5, 0xa5a5a5a5 ) + SV_ELWIDTH_TEST( 3, 2, 3, 3, 1, 1, 1, + 0x00004000, 0x0000aaaa, 0x0000fd7e ) +/* SV_ELWIDTH_TEST( 3, 1, 1, 2, 1, 1, 1, 0xa5a5001900110009, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 ) SV_ELWIDTH_TEST( 3, 1, 1, 1, 1, 1, 1,