From: lkcl <lkcl@web>
Date: Fri, 2 Sep 2022 17:06:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~730
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bc7e254de03c01ed30e96903ee675fd49753811;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 5eb0a5716..47c3c8712 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -161,7 +161,8 @@ With element-width overrides being meaningless for Condition
 Register Fields, bits 4 thru 7 of SVP64 RM may be used for additional
 Mode bits.
 
-SVP64 RM `MODE` (includes `ELWIDTH` and `ELWIDTH_SRC` bits) for Branch
+SVP64 RM `MODE` (includes repurposing `ELWIDTH` bits 4:5,
+and `ELWIDTH_SRC` bits 6-7 for *alternate* uses) for Branch
 Conditional:
 
 | 4 | 5 | 6 | 7 | 17 | 18 | 19 | 20 |  21 | 22  23 |  description     |