From: Tim Newsome <tim@sifive.com>
Date: Tue, 27 Jun 2017 17:53:16 +0000 (-0700)
Subject: Tolerate missing misa register.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bca79a33e902a7c43626ef89c51ecb9efd2125e;p=riscv-tests.git

Tolerate missing misa register.

At least in the test programs. There are other places where this causes
trouble as well.
---

diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index c9e319c..ff8ae30 100755
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -27,7 +27,9 @@ trap_vector:
   j trap_entry
 
 handle_reset:
-  la t0, trap_entry
+  // If misa doesn't exist (or is following an old spec where it has a
+  // different number), skip the next block.
+  la t0, 3f
   csrw mtvec, t0
   csrwi mstatus, 0
 
@@ -48,6 +50,10 @@ handle_reset:
   csrwi medeleg, 0
 2:
   csrwi mie, 0
+3:
+  la t0, trap_entry
+  csrw mtvec, t0
+  csrwi mstatus, 0
 
   # initialize global pointer
 .option push