From: Sebastien Bourdeauducq Date: Wed, 3 Jul 2019 09:42:48 +0000 (+0800) Subject: add KC705 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bcb6099ce4a996931643113a512468efc59bf19;p=nmigen-boards.git add KC705 --- diff --git a/nmigen_boards/kc705.py b/nmigen_boards/kc705.py new file mode 100644 index 0000000..2f3385e --- /dev/null +++ b/nmigen_boards/kc705.py @@ -0,0 +1,45 @@ +import os +import subprocess + +from nmigen.build import * +from nmigen.vendor.xilinx_7series import * +from .dev import * + + +__all__ = ["KC705Platform"] + + +class KC705Platform(Xilinx7SeriesPlatform): + device = "xc7k325t" + package = "ffg900" + speed = "2" + resources = [ + Resource("clk156", 0, DiffPairs("K28", "K29", dir="i"), + Clock(156e6), Attrs(IOSTANDARD="LVDS_25")), + + Resource("user_led", 0, Pins("AB8", dir="o"), Attrs(IOSTANDARD="LVCMOS15")), + Resource("user_led", 1, Pins("AA8", dir="o"), Attrs(IOSTANDARD="LVCMOS15")), + Resource("user_led", 2, Pins("AC9", dir="o"), Attrs(IOSTANDARD="LVCMOS15")), + Resource("user_led", 3, Pins("AB9", dir="o"), Attrs(IOSTANDARD="LVCMOS15")), + Resource("user_led", 4, Pins("AE26", dir="o"), Attrs(IOSTANDARD="LVCMOS15")), + Resource("user_led", 5, Pins("G19", dir="o"), Attrs(IOSTANDARD="LVCMOS15")), + Resource("user_led", 6, Pins("E18", dir="o"), Attrs(IOSTANDARD="LVCMOS15")), + Resource("user_led", 7, Pins("F16", dir="o"), Attrs(IOSTANDARD="LVCMOS15")), + + UARTResource(0, + rx="M19", tx="K24", + attrs=Attrs(IOSTANDARD="LVCMOS33") + ), + ] + connectors = [] + + def toolchain_program(self, products, name): + openocd = os.environ.get("OPENOCD", "openocd") + with products.extract("{}.bit".format(name)) as bitstream_filename: + subprocess.run([openocd, "-c", + "source [find board/kc705.cfg]; init; pld load 0 bitstream_filename; exit".format(bitstream_filename)], check=True) + + +if __name__ == "__main__": + from ._blinky import build_and_program + build_and_program(KC705Platform, "clk156")