From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 01:15:28 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig
X-Git-Tag: working-ls180~1237^2~163^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bd2bfa737266c739000d149955b96966276eb8d;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig
---

0bd2bfa737266c739000d149955b96966276eb8d
diff --cc techlibs/xilinx/synth_xilinx.cc
index 08d74cd3b,53eee7962..5820d6d61
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -197,9 -202,9 +206,13 @@@ struct SynthXilinxPass : public Pas
  				nodram = true;
  				continue;
  			}
+ 			if (args[argidx] == "-nosrl") {
+ 				nosrl = true;
+ 				continue;
++            }
 +			if (args[argidx] == "-abc9") {
 +				abc = "abc9";
 +				continue;
  			}
  			break;
  		}
@@@ -283,10 -302,15 +310,15 @@@
  
  		if (check_label(active, run_from, run_to, "map_luts"))
  		{
- 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
+ 			Pass::call(design, "opt -full");
+ 			Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
 -			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 +			Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
  			Pass::call(design, "clean");
- 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
+ 			// This shregmap call infers fixed length shift registers after abc
+ 			//   has performed any necessary retiming
+ 			if (!nosrl)
+ 				Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
+ 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
  			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
  					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
  			Pass::call(design, "clean");