From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 08:40:31 +0000 (+0200)
Subject: Added RTLIL::Design::modules()
X-Git-Tag: yosys-0.4~399
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bd8fafbd2f36f59327289e52abf962c166dab8b;p=yosys.git

Added RTLIL::Design::modules()
---

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7249f0cad..6eb52cf2d 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -340,6 +340,7 @@ struct RTLIL::Selection
 
 struct RTLIL::Design
 {
+	int refcount_modules_;
 	std::map<RTLIL::IdString, RTLIL::Module*> modules_;
 
 	std::vector<RTLIL::Selection> selection_stack;
@@ -348,6 +349,8 @@ struct RTLIL::Design
 
 	~Design();
 
+	RTLIL::ObjRange<RTLIL::Module*> modules() { return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_); }
+
 	void check();
 	void optimize();