From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 15:22:29 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2322
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0be256a6e8d8ad10073f0011aa0a729cb2363dc3;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 3fe97c0fe..6a36c5765 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -74,7 +74,7 @@ which illustrates a catastrophic rabbit-hole taken by Industry Giants
 ARM, Intel, AMD, since the 90s (over 3 decades) whereby SIMD, an
 Order(N^6) opcode proliferation nightmare, with its mantra "make it
 easy for hardware engineers, let software sort out the mess" literally
-overwhelming programmers.  Specialists charging
+overwhelming programmers with thousands of instructions. Specialists charging
 clients for assembly-code Optimisation Services are finding that AVX-512,
 to take an
 example, is anything but optimal: overall performance of AVX-512 actually