From: Chung-Ju Wu Date: Sun, 27 May 2018 06:52:48 +0000 (+0000) Subject: [NDS32] Implement bswapsi2 and bswaphi2 patterns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0be3bad7054256f009a066cce34b4cca12f3b86f;p=gcc.git [NDS32] Implement bswapsi2 and bswaphi2 patterns. gcc/ * config/nds32/nds32.md (bswapsi2, bswaphi2): New patterns. From-SVN: r260804 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 73c578165f3..293856b0888 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2018-05-27 Chung-Ju Wu + + * config/nds32/nds32.md (bswapsi2, bswaphi2): New patterns. + 2018-05-27 Chung-Ju Wu * config/nds32/nds32.c (nds32_attribute_table): Add "no_prologue". diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 63e4efe23da..66ef03327f4 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -2180,6 +2180,26 @@ [(set_attr "type" "alu") (set_attr "length" "4")] ) + +(define_expand "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "" +{ + emit_insn (gen_unspec_wsbh (operands[0], operands[1])); + emit_insn (gen_rotrsi3 (operands[0], operands[0], GEN_INT (16))); + DONE; +}) + +(define_insn "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=r") + (bswap:HI (match_operand:HI 1 "register_operand" "r")))] + "" + "wsbh\t%0, %1" + [(set_attr "type" "alu") + (set_attr "length" "4")] +) + ;; ---------------------------------------------------------------------------- ;; Patterns for exception handling