From: Richard Henderson Date: Thu, 14 Nov 2019 13:44:05 +0000 (+0000) Subject: arm: Fix the "c" constraint X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0be72bfaeb94de26a8fcdac98aabe42139f98bbb;p=gcc.git arm: Fix the "c" constraint The existing definition using register class CC_REG does not work because CC_REGNUM does not support normal modes, and so fails to match register_operand. Use a non-register constraint and the cc_register predicate instead. * config/arm/constraints.md (c): Use cc_register predicate. From-SVN: r278224 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ea547f7cf40..85fa8924c57 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,7 @@ 2019-11-14 Richard Henderson + * config/arm/constraints.md (c): Use cc_register predicate. + * config/aarch64/constraints.md (c): New constraint. 2019-11-14 Jan Hubicka diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index b76de81b85c..e02b678d26d 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -94,8 +94,9 @@ "@internal Thumb only. The union of the low registers and the stack register.") -(define_register_constraint "c" "CC_REG" - "@internal The condition code register.") +(define_constraint "c" + "@internal The condition code register." + (match_operand 0 "cc_register")) (define_register_constraint "Cs" "CALLER_SAVE_REGS" "@internal The caller save registers. Useful for sibcalls.")