From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 15:43:25 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2305
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bf6fd6978f7fbadeab6bc34b7e93e57c43fa986;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 35ef65f22..015fcc2cd 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -15,7 +15,8 @@
 
 Inventing a new Scalar ISA from scratch is over a decade-long task
 including simulators and compilers: OpenRISC 1200 took 12 years to
-mature.  A Vector or Packed SIMD ISA to reach stable *general-purpose*
+mature.  Stable ISAs require Standards and Compliance Suites that
+take more. A Vector or Packed SIMD ISA to reach stable *general-purpose*
 auto-vectorisation compiler support has never been achieved in the
 history of computing, not with the combined resources of ARM, Intel,
 AMD, MIPS, Sun Microsystems, SGI, Cray, and many more. (*Hand-crafted