From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 07:35:14 +0000 (+0200)
Subject: Add support for $assert/$assume/$cover to write_verilog
X-Git-Tag: yosys-0.9~141^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0bf9d0087c43f9db3d56cb2bed17268def21eb67;p=yosys.git

Add support for $assert/$assume/$cover to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 9967482d6..1c65e79b7 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1242,6 +1242,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type.in("$assert", "$assume", "$cover"))
+	{
+		f << stringf("%s" "always @* if (", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\EN"));
+		f << stringf(") %s(", cell->type.c_str()+1);
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(");\n");
+		return true;
+	}
+
 	// FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_
 	// FIXME: $sr, $dlatch, $memrd, $memwr, $fsm