From: Alan Modra Date: Thu, 30 Jan 2020 11:29:20 +0000 (+1030) Subject: ubsan: m32c: left shift of negative value X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c115f8483ac32dc95fde902cac8c8bb99f9c3be;p=binutils-gdb.git ubsan: m32c: left shift of negative value More nonsense fixing "bugs" with left shifts of signed values. Yes, the C standard does say this is undefined (and right shifts of signed values are implementation defined BTW) but in practice there is no problem with current machines. 1's complement is a thing of the past. cpu/ * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting. (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise. (f-dst32-rn-prefixed-QI): Likewise. (f-dsp-32-s32): Mask before shifting left. (f-dsp-48-u32, f-dsp-48-s32): Likewise. (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than shifting left. (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise. (h-gr-SI): Mask before shifting. opcodes/ * m32c-ibld.c: Regenerate. --- diff --git a/cpu/ChangeLog b/cpu/ChangeLog index b6a1e3a396a..3e8f019e353 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,15 @@ +2020-01-30 Alan Modra + + * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting. + (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise. + (f-dst32-rn-prefixed-QI): Likewise. + (f-dsp-32-s32): Mask before shifting left. + (f-dsp-48-u32, f-dsp-48-s32): Likewise. + (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than + shifting left. + (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise. + (h-gr-SI): Mask before shifting. + 2020-01-30 Jose E. Marchesi * bpf.cpu (define-alu-insn-un): The unary BPF instructions diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index 1e630a4a51a..48b5acdfbd0 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -240,7 +240,7 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; QI mode gr encoding for m32c is different than for m16c. The hardware @@ -252,7 +252,7 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; HI mode gr encoding for m32c is different than for m16c. The hardware @@ -316,11 +316,11 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) (df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; HI mode gr encoding for m32c is different than for m16c. The hardware @@ -720,22 +720,22 @@ (ext INT (or SI (or SI - (and (srl value 24) #x000000ff) - (and (srl value 8) #x0000ff00)) + (and (srl value 24) #x00ff) + (and (srl value 8) #xff00)) (or SI - (and (sll value 8) #x00ff0000) - (and (sll value 24) #xff000000))))) + (sll (and value #xff00) 8) + (sll (and value #x00ff) 24))))) ;; extract ((value pc) (ext INT (or SI (or SI - (and (srl value 24) #x000000ff) - (and (srl value 8) #x0000ff00)) + (and (srl value 24) #x00ff) + (and (srl value 8) #xff00)) (or SI - (and (sll value 8) #x00ff0000) - (and (sll value 24) #xff000000))))) + (sll (and value #xff00) 8) + (sll (and value #x00ff) 24))))) ) (dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT @@ -746,7 +746,7 @@ ) (sequence () ; extract (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) + (sll (and (ifield f-dsp-64-u16) #xffff) 16))) ) ) @@ -758,7 +758,7 @@ ) (sequence () ; extract (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) + (sll (and (ifield f-dsp-64-u16) #xffff) 16))) ) ) @@ -827,7 +827,7 @@ (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3)) ) (sequence () ; extract - (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3) + (set (ifield f-bitbase32-16-s11-unprefixed) (or (mul (ifield f-dsp-16-s8) 8) (ifield f-bitno32-unprefixed))) ) ) @@ -885,7 +885,7 @@ (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3)) ) (sequence () ; extract - (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3) + (set (ifield f-bitbase32-24-s11-prefixed) (or (mul (ifield f-dsp-24-s8) 8) (ifield f-bitno32-prefixed))) ) ) @@ -913,7 +913,7 @@ ) (sequence () ; extract (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) - (or (sll (ifield f-dsp-32-s8) 11) + (or (mul (ifield f-dsp-32-s8) 2048) (ifield f-bitno32-prefixed)))) ) ) @@ -1075,7 +1075,7 @@ (indices keyword "" (("r2r0" 0) ("r3r1" 1))) (get (index) (or SI (and (reg h-gr index) #xffff) - (and (sll (reg h-gr (add index 2)) 16) #xffff0000))) + (sll (and (reg h-gr (add index 2)) #xffff) 16))) (set (index newval) (sequence () (set (reg h-gr index) (and newval #xffff)) (set (reg h-gr (add index 2)) (srl newval 16))))) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 13333aa8b30..975d7e6bfb4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2020-01-30 Alan Modra + + * m32c-ibld.c: Regenerate. + 2020-01-30 Jose E. Marchesi * bpf-opc.c: Regenerate. diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c index 976b70b7a9b..7083a575e1a 100644 --- a/opcodes/m32c-ibld.c +++ b/opcodes/m32c-ibld.c @@ -609,14 +609,14 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_BIT32RNPREFIXED : { long value = fields->f_dst32_rn_prefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); } break; case M32C_OPERAND_BIT32RNUNPREFIXED : { long value = fields->f_dst32_rn_unprefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); } break; @@ -1191,7 +1191,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DST32RNPREFIXEDQI : { long value = fields->f_dst32_rn_prefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); } break; @@ -1212,7 +1212,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DST32RNUNPREFIXEDQI : { long value = fields->f_dst32_rn_unprefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); } break; @@ -1317,7 +1317,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_IMM_32_SI : { long value = fields->f_dsp_32_s32; - value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000))))))); + value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) & (65280))) << (8))) | (((((value) & (255))) << (24))))))); errmsg = insert_normal (cd, value, 0|(1<f_src32_rn_prefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer); } break; @@ -1624,7 +1624,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_SRC32RNUNPREFIXEDQI : { long value = fields->f_src32_rn_unprefixed_QI; - value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + value = (((((~ (((value) << (1))))) & (2))) | (((((USI) (value) >> (1))) & (1)))); errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer); } break; @@ -1851,7 +1851,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); if (length <= 0) break; { - FLD (f_bitbase32_16_s11_unprefixed) = ((((FLD (f_dsp_16_s8)) << (3))) | (FLD (f_bitno32_unprefixed))); + FLD (f_bitbase32_16_s11_unprefixed) = ((((FLD (f_dsp_16_s8)) * (8))) | (FLD (f_bitno32_unprefixed))); } } break; @@ -1923,7 +1923,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_24_s8); if (length <= 0) break; { - FLD (f_bitbase32_24_s11_prefixed) = ((((FLD (f_dsp_24_s8)) << (3))) | (FLD (f_bitno32_prefixed))); + FLD (f_bitbase32_24_s11_prefixed) = ((((FLD (f_dsp_24_s8)) * (8))) | (FLD (f_bitno32_prefixed))); } } break; @@ -1936,7 +1936,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_32_s8); if (length <= 0) break; { - FLD (f_bitbase32_24_s19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_s8)) << (11))) | (FLD (f_bitno32_prefixed))))); + FLD (f_bitbase32_24_s19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_s8)) * (2048))) | (FLD (f_bitno32_prefixed))))); } } break; @@ -2480,7 +2480,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, { long value; length = extract_normal (cd, ex_info, insn_value, 0|(1<> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000))))))); + value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) & (65280))) << (8))) | (((((value) & (255))) << (24))))))); fields->f_dsp_32_s32 = value; } break; @@ -2539,7 +2539,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, } if (length <= 0) break; { - FLD (f_dsp_48_s32) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u16)) << (16))) & (0xffff0000)))); + FLD (f_dsp_48_s32) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u16)) & (65535))) << (16)))); } } break;