From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 30 Sep 2015 09:06:31 +0000 (+0800)
Subject: test/fifo: do not use Record
X-Git-Tag: 24jan2021_ls180~2099^2~3^2~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c1e1c97690bef682d8ebb9defead37ec5332b14;p=litex.git

test/fifo: do not use Record
---

diff --git a/migen/test/test_fifo.py b/migen/test/test_fifo.py
index 48ffc963..6dfc9c4e 100644
--- a/migen/test/test_fifo.py
+++ b/migen/test/test_fifo.py
@@ -10,19 +10,15 @@ from migen.test.support import SimCase
 class SyncFIFOCase(SimCase, unittest.TestCase):
     class TestBench(Module):
         def __init__(self):
-            self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)
+            self.submodules.dut = SyncFIFO(64, 2)
 
             self.sync += [
                 If(self.dut.we & self.dut.writable,
-                    self.dut.din.a.eq(self.dut.din.a + 1),
-                    self.dut.din.b.eq(self.dut.din.b + 2)
+                    self.dut.din[:32].eq(self.dut.din[:32] + 1),
+                    self.dut.din[32:].eq(self.dut.din[32:] + 2)
                 )
             ]
 
-    def test_sizes(self):
-        self.assertEqual(len(self.tb.dut.din_bits), 64)
-        self.assertEqual(len(self.tb.dut.dout_bits), 64)
-
     def test_run_sequence(self):
         seq = list(range(20))
         def gen():
@@ -36,8 +32,8 @@ class SyncFIFOCase(SimCase, unittest.TestCase):
                         i = seq.pop(0)
                     except IndexError:
                         break
-                    self.assertEqual((yield self.tb.dut.dout.a), i)
-                    self.assertEqual((yield self.tb.dut.dout.b), i*2)
+                    self.assertEqual((yield self.tb.dut.dout[:32]), i)
+                    self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
                 yield
         self.run_with(gen())
 
@@ -48,13 +44,13 @@ class SyncFIFOCase(SimCase, unittest.TestCase):
                 yield self.tb.dut.we.eq(cycle % 2 == 0)
                 yield self.tb.dut.re.eq(cycle % 7 == 0)
                 yield self.tb.dut.replace.eq(
-                    (yield self.tb.dut.din.a) % 5 == 1)
+                    (yield self.tb.dut.din[:32]) % 5 == 1)
                 if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
                     try:
                         i = seq.pop(0)
                     except IndexError:
                         break
-                    self.assertEqual((yield self.tb.dut.dout.a), i)
-                    self.assertEqual((yield self.tb.dut.dout.b), i*2)
+                    self.assertEqual((yield self.tb.dut.dout[:32]), i)
+                    self.assertEqual((yield self.tb.dut.dout[32:]), i*2)
                 yield
         self.run_with(gen())