From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 9 Aug 2019 07:27:32 +0000 (+0200)
Subject: cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
X-Git-Tag: 24jan2021_ls180~1057
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c287b11ba11b24eaba6cf19282ac7b074720b3c;p=litex.git

cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 6c8525f6..037d367d 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -214,9 +214,9 @@ class S7PLL(XilinxClocking):
         XilinxClocking.__init__(self)
         self.divclk_divide_range = (1, 56+1)
         self.vco_freq_range = {
-            -1: (800e6, 2133e6),
+            -1: (800e6, 1600e6),
             -2: (800e6, 1866e6),
-            -3: (800e6, 1600e6),
+            -3: (800e6, 2133e6),
         }[speedgrade]
 
     def do_finalize(self):