From: Sebastien Bourdeauducq Date: Mon, 26 Nov 2012 17:19:41 +0000 (+0100) Subject: tb/asmicon/asmicon_wb: more complete testing by default X-Git-Tag: 24jan2021_ls180~3074 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c29775a8f184c7ac0bf22838c107b39b458ed1c;p=litex.git tb/asmicon/asmicon_wb: more complete testing by default --- diff --git a/tb/asmicon/asmicon_wb.py b/tb/asmicon/asmicon_wb.py index 78aaddf6..28f6dc28 100644 --- a/tb/asmicon/asmicon_wb.py +++ b/tb/asmicon/asmicon_wb.py @@ -10,18 +10,18 @@ from common import sdram_phy, sdram_geom, sdram_timing, DFILogger l2_size = 8192 # in bytes def my_generator(): - #for x in range(20): - #t = TWrite(x, x) - #yield t - #print(str(t) + " delay=" + str(t.latency)) for x in range(20): - t = TRead(4194304//4 + x) + t = TWrite(x, x) + yield t + print(str(t) + " delay=" + str(t.latency)) + for x in range(20): + t = TRead(x) + yield t + print(str(t) + " delay=" + str(t.latency)) + for x in range(20): + t = TRead(x+l2_size//4) yield t print(str(t) + " delay=" + str(t.latency)) - #for x in range(20): - #t = TRead(x+l2_size//4) - #yield t - #print(str(t) + " delay=" + str(t.latency)) def main(): controller = ASMIcon(sdram_phy, sdram_geom, sdram_timing)