From: lkcl <lkcl@web>
Date: Fri, 26 Aug 2022 14:48:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~755
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c2b2e45a345407917af1d005537877bd66bf5af;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index fd8327225..dbc08e9b2 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -148,6 +148,16 @@ from different sources is as follows:
 The reasoning here is that the opportunity to set RT equal to the
 immediate `SVi+1` is sacrificed in favour of setting from CTR.
 
+# Rc=1
+
+CR Field 0, when `Rc=1`, may be set even if `RT=0`. The reason is that
+overflow may occur: `VL`, if set either from an immediate or from `CTR`,
+may not exceed `MAXVL`, and if it is, `CR0.SO` must be set.
+
+Additionally, in reality it is **`VL`** being set. Therefore, rather
+than `CR0` testing `RT` when `Rc=1`, CR0.EQ is set if `VL=0`, CR0.GE
+is set if `VL` is non-zero.
+
 # Vertical First Mode
 
 Vertical First is effectively like an implicit single bit predicate