From: whitequark Date: Fri, 21 Dec 2018 02:01:27 +0000 (+0000) Subject: memory_collect: do not truncate 'x from \INIT. X-Git-Tag: yosys-0.9~358^2~3^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c318e7db513bed1844f594ae780f854ed08e18f;p=yosys.git memory_collect: do not truncate 'x from \INIT. The semantics of an RTLIL constant that has less bits than its declared bit width is zero padding. Therefore, if the output of memory_collect will be used for simulation, truncating 'x from the end of \INIT will produce incorrect simulation results. --- diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 70d98713c..369fcc84e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -184,9 +184,6 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->parameters["\\OFFSET"] = Const(memory->start_offset); mem->parameters["\\SIZE"] = Const(memory->size); mem->parameters["\\ABITS"] = Const(addr_bits); - - while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx) - init_data.bits.pop_back(); mem->parameters["\\INIT"] = init_data; log_assert(sig_wr_clk.size() == wr_ports);