From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 1 Jul 2020 16:41:16 +0000 (+0100)
Subject: attempting to add SPRs to rfid test
X-Git-Tag: div_pipeline~184
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c3689e8f95c8b2d08100055c9b9c3711d366f1c;p=soc.git

attempting to add SPRs to rfid test
---

diff --git a/libreriscv b/libreriscv
index bd0a43e8..1d09d245 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit bd0a43e88d6ee58a5d331d70e182cbadca54d7b8
+Subproject commit 1d09d2455985e602a5799e1fafac5cea6b1cb72d
diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index a7ec70d1..488df5ce 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -9,7 +9,8 @@ from functools import wraps
 from soc.decoder.orderedset import OrderedSet
 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
-from soc.decoder.power_enums import spr_dict, XER_bits, insns, InternalOp
+from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
+                                     insns, InternalOp)
 from soc.decoder.helpers import exts, trunc_div, trunc_rem
 from collections import namedtuple
 import math
@@ -186,7 +187,14 @@ class SPR(dict):
     def __init__(self, dec2, initial_sprs={}):
         self.sd = dec2
         dict.__init__(self)
-        self.update(initial_sprs)
+        for key, v in initial_sprs.items():
+            if isinstance(key, SelectableInt):
+                key = key.value
+            key = special_sprs.get(key, key)
+            info = spr_byname[key]
+            if not isinstance(v, SelectableInt):
+                v = SelectableInt(v, info.length)
+            self[key] = v
 
     def __getitem__(self, key):
         # if key in special_sprs get the special spr, otherwise return key
@@ -271,7 +279,9 @@ class ISACaller:
         # "undefined", just set to variable-bit-width int (use exts "max")
         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
 
-        self.namespace = {'GPR': self.gpr,
+        self.namespace = {}
+        self.namespace.update(self.spr)
+        self.namespace.update({'GPR': self.gpr,
                           'MEM': self.mem,
                           'SPR': self.spr,
                           'memassign': self.memassign,
@@ -282,7 +292,8 @@ class ISACaller:
                           'undefined': self.undefined,
                           'mode_is_64bit': True,
                           'SO': XER_bits['SO']
-                          }
+                          })
+
 
         # field-selectable versions of Condition Register TODO check bitranges?
         self.crl = []
diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index f179f2ce..931101ec 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -294,10 +294,12 @@ class CROutSel(Enum):
 spr_csv = get_csv("sprs.csv")
 spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length')
 spr_dict = {}
+spr_byname = {}
 for row in spr_csv:
     info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
                     priv_mfspr=row['priv_mfspr'], length=int(row['len']))
     spr_dict[int(row['Idx'])] = info
+    spr_byname[row['SPR']] = info
 fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 SPR = Enum('SPR', fields)
 
diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 4f1af455..1d3c7f8d 100644
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -82,7 +82,8 @@ class TrapTestCase(FHDLTestCase):
         lst = ["rfid"]
         initial_regs = [0] * 32
         initial_regs[1] = 1
-        self.run_tst_program(Program(lst), initial_regs)
+        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
+        self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 
     def test_0_trap_eq_imm(self):
         insns = ["tw", "td"]