From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 16:55:14 +0000 (-0700)
Subject: Count $_NOT_ cells turned into $luts
X-Git-Tag: working-ls180~881^2^2~261
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c3ed73dade2488d0add1a3e6e82b148171f2d66;p=yosys.git

Count $_NOT_ cells turned into $luts
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 4347c3789..53b0b8bbe 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -584,7 +584,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					log_assert(wire);
 					module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
 				}
-				else if (!lut_costs.empty() || !lut_file.empty()) {
+				else {
 					RTLIL::Cell* driving_lut = nullptr;
 					// ABC can return NOT gates that drive POs
 					if (!a_bit.wire->port_input) {
@@ -622,12 +622,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 								RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
 								driver_lut);
 					}
-				}
-				else {
-					cell = module->addCell(remap_name(c->name), "$_NOT_");
-					cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
-					cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
-					cell_stats[RTLIL::unescape_id(c->type)]++;
+					cell_stats["$lut"]++;
 				}
 				if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
 				continue;