From: Ali Saidi <Ali.Saidi@arm.com>
Date: Mon, 23 Aug 2010 16:18:40 +0000 (-0500)
Subject: ARM: Exclusive accesses must be double word aligned
X-Git-Tag: stable_2012_02_02~902
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c434b7f5650be8e742199e2d1efb5d642e210c5;p=gem5.git

ARM: Exclusive accesses must be double word aligned
---

diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index cc6b6351b..6919bbca4 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -206,7 +206,9 @@ let {{
             # Add memory request flags where necessary
             if self.flavor == "exclusive":
                 self.memFlags.append("Request::LLSC")
-            self.memFlags.append("ArmISA::TLB::AlignWord")
+                self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
+            else:
+                self.memFlags.append("ArmISA::TLB::AlignWord")
 
             # Disambiguate the class name for different flavors of loads
             if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 589758529..5b0e5b132 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -225,9 +225,11 @@ let {{
             self.Name = self.nameFunc(self.post, self.add, self.writeback)
 
             # Add memory request flags where necessary
-            self.memFlags.append("ArmISA::TLB::AlignWord")
             if self.flavor == "exclusive":
                 self.memFlags.append("Request::LLSC")
+                self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
+            else:
+                self.memFlags.append("ArmISA::TLB::AlignWord")
 
             # Disambiguate the class name for different flavors of stores
             if self.flavor != "normal":