From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 04:13:25 +0000 (-0800)
Subject: Add -D DFF_MODE to abc9_map test
X-Git-Tag: working-ls180~881^2^2~45
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c4be94a02a70de495343258ecda19eb20b3616b;p=yosys.git

Add -D DFF_MODE to abc9_map test
---

diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys
index 6823589f1..4a7b9384a 100644
--- a/tests/arch/xilinx/abc9_map.ys
+++ b/tests/arch/xilinx/abc9_map.ys
@@ -6,7 +6,7 @@ endmodule
 EOT
 design -save gold
 
-techmap -map +/xilinx/abc9_map.v -max_iter 1
+techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
 techmap -map +/xilinx/abc9_unmap.v
 select -assert-count 1 t:FDSE
 select -assert-count 1 t:FDSE_1
@@ -29,7 +29,7 @@ endmodule
 EOT
 design -save gold
 
-techmap -map +/xilinx/abc9_map.v -max_iter 1
+techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
 techmap -map +/xilinx/abc9_unmap.v
 select -assert-count 1 t:FDRE
 select -assert-count 1 t:FDRE_1
@@ -52,7 +52,7 @@ endmodule
 EOT
 design -save gold
 
-techmap -map +/xilinx/abc9_map.v -max_iter 1
+techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
 techmap -map +/xilinx/abc9_unmap.v
 select -assert-count 1 t:FDCE
 select -assert-count 1 t:FDCE_1
@@ -76,7 +76,7 @@ endmodule
 EOT
 design -save gold
 
-techmap -map +/xilinx/abc9_map.v -max_iter 1
+techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
 techmap -map +/xilinx/abc9_unmap.v
 select -assert-count 1 t:FDPE
 techmap -autoproc -map +/xilinx/cells_sim.v