From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jun 2020 16:52:42 +0000 (+0100)
Subject: add write-regs encoding to regspec decoder
X-Git-Tag: div_pipeline~651
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c51694224272763f482e9e4a1d5a071d973e2cf;p=soc.git

add write-regs encoding to regspec decoder
---

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 632c19fc..c85db645 100644
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -131,6 +131,10 @@ def regspec_decode(e, regfile, name):
             return e.read_reg2.ok, 1<<e.read_reg2.data, None
         if name == 'rc': # RS
             return e.read_reg3.ok, 1<<e.read_reg3.data, None
+        if name == 'o': # RT
+            return e.write_reg.ok, None, 1<<e.write_reg.data
+        if name == 'o1': # RA (update mode: LD/ST EA)
+            return e.write_ea.ok, None, 1<<e.write_ea.data
 
     if regfile == 'CR':
         # CRRegs register numbering is *unary* encoded