From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 14 Jun 2013 15:57:43 +0000 (+0200)
Subject: bus/asmibus: fix slot aging timer
X-Git-Tag: 24jan2021_ls180~2099^2~557
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c52c08989d3bee4b78572efc69ac583bd0fa757;p=litex.git

bus/asmibus: fix slot aging timer
---

diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py
index e1141e98..2ddabbe8 100644
--- a/migen/bus/asmibus.py
+++ b/migen/bus/asmibus.py
@@ -9,10 +9,11 @@ from migen.sim.generic import Proxy
 
 class Slot(Module):
 	def __init__(self, aw, time):
+		self.time = time
 		self.state = Signal(2)
 		self.we = Signal()
 		self.adr = Signal(aw)
-		if time:
+		if self.time:
 			self.mature = Signal()
 		
 		self.allocate = Signal()
@@ -32,14 +33,14 @@ class Slot(Module):
 			If(self.process, self.state.eq(SLOT_PROCESSING)),
 			If(self.call, self.state.eq(SLOT_EMPTY))
 		]
-		if time:
-			_counter = Signal(max=time+1)
-			self.comb += self.mature.eq(self._counter == 0)
+		if self.time:
+			counter = Signal(max=self.time+1)
+			self.comb += self.mature.eq(counter == 0)
 			self.sync += [
 				If(self.allocate,
-					self._counter.eq(self.time)
-				).Elif(self._counter != 0,
-					self._counter.eq(self._counter - 1)
+					counter.eq(self.time)
+				).Elif(counter != 0,
+					counter.eq(counter - 1)
 				)
 			]