From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Jun 2019 07:38:24 +0000 (+0100)
Subject: discussion tidyup
X-Git-Tag: convert-csv-opcode-to-binary~4466
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c5a3dbb43ca3ba04308182c6e4a21b58b3343ac;p=libreriscv.git

discussion tidyup
---

diff --git a/simple_v_extension/sv_prefix_proposal/discussion.mdwn b/simple_v_extension/sv_prefix_proposal/discussion.mdwn
index 279543e0a..215f528ab 100644
--- a/simple_v_extension/sv_prefix_proposal/discussion.mdwn
+++ b/simple_v_extension/sv_prefix_proposal/discussion.mdwn
@@ -61,7 +61,9 @@ Example pseudocode:
         rd[i * DESTSUBVL + 0] = rs1[i * SRCSUBVL + elements[0]];
     }
 
---
+> ok, i like that idea - adding to TODO list
+
+----
 
 What is SUBVL and how does it work
 
@@ -103,7 +105,7 @@ performs the following operation:
         }
     }
 
---
+----
 
 SVorig goes to a lot of effort to make VL 1<= MAXVL and MAXVL 1..64
 where both CSRs may be stored internally in only 6 bits.
@@ -131,7 +133,7 @@ One related idea would to support VL > XLEN but to only allow unpredicated
 instructions when VL > XLEN. This would allow later implementing register
 pairs/triplets/etc. as predicates as an extension.
 
---
+----
 
 Is MV.X good enough a substitute for swizzle?
 
@@ -143,18 +145,18 @@ doesn't need to pessimize. Additionally, swizzles almost always have constant
 element selectors. MV.X is meant more as a last-resort instruction that is
 better than load/store, but worse than everything else.
 
---
+----
 
 Is vectorised srcbase ok as a gather scatter and ok substitute for
 register stride? 5 dependency registers (reg stride being the 5th)
 is quite scary
 
---
+----
 
 Why are integer conversion instructions needed, when the main SV spec
 covers them by allowing elwidth to be set on both src and dest regs?
 
---
+----
 
 Why are the SETVL rules so complex? What is the reason, how are loops
 carried out?
@@ -175,7 +177,7 @@ maxVL CSR needed for just SVPrefix.
 > hardcoded MVL baked into the actual hardware.
 > That results in loss of flexibility and defeats the purpose of SV. 
 
---
+----
 
 With SUBVL (sub vector len) being both a CSR and also part of the 48/64
 bit opcode, how does that work?
@@ -196,7 +198,7 @@ all the state for context-switching and exception handling.
 > STATE CSR if needed is a workable compromise that
 > does not result in huge CSR proliferation
 
---
+----
 
 What are the interaction rules when a 48/64 prefix opcode has a rd/rs
 that already has a Vector Context for either predication or a register?
@@ -211,7 +213,7 @@ Possible solution, svlen and VLtyp allowed to share STATE CSR however
 programmer becomes responsible for push and pop of state during use of
 a sequence of P48 and P64 ops.
 
---
+----
 
 Can bit 60 of P64 be put to use (in all but the FR4 case)?