From: programmerjake <programmerjake@web>
Date: Thu, 23 Apr 2020 05:43:23 +0000 (+0100)
Subject: add link to alternative memory interface idea
X-Git-Tag: convert-csv-opcode-to-binary~2816
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c63205bf1e7b139004f3859e85a889c52fc4a71;p=libreriscv.git

add link to alternative memory interface idea
---

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index 85f84dac3..ac02a3248 100644
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -38,6 +38,10 @@ Basic diagram:
 * Memory is the silicon-proven OpenCores [SDRAM|sdram] interface,
   and it is Wishbone compliant.
 
+## Alternative Design Idea
+
+[[alternative-design-idea]]
+
 # 28-45nm Quad-Core SoC
 
 This is full SMP, requires analog PLLs, clock gating, full SMP