From: Sadullah Canakci Date: Sat, 2 May 2020 04:10:06 +0000 (-0400) Subject: Update README.md X-Git-Tag: 24jan2021_ls180~403^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c770e0683f39cad480e1a51667159e0ae4ef80f;p=litex.git Update README.md --- diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 52023e53..d97b68a3 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -46,11 +46,10 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) -# sys_clk_freq = int(50e6) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) -# self.add_constant("UART_POLLING",None) + # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), diff --git a/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md b/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md deleted file mode 100644 index 47ea7373..00000000 --- a/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md +++ /dev/null @@ -1,23 +0,0 @@ -# Getting started - -## Running BP in LiteX - -cd $LITEX/litex/tools # the folder where litex simulator resides - -./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP --threads 4 --opt-level=O0 --trace --trace-start 0 - -#The above command will generate a dut.vcd file under build/BP/gateware folder. gtkwave works fine with the generated dut.vcd. - -## Additional Information - -The BlackParrot resides in $BP/pre-alpha-release/ - -core.py in $BP folder is the wrapper that integrates BP into LiteX. - -flist.verilator in $BP is all the files that litex_sim fetches for simulation. - -The top module is $BP_FPGA_DIR/ExampleBlackParrotSystem.v - -The transducer for wishbone communication is $BP_FPGA_DIR/bp2wb_convertor.v - - diff --git a/litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md b/litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md new file mode 100644 index 00000000..55ec62e2 --- /dev/null +++ b/litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md @@ -0,0 +1,24 @@ +# Getting started (TODO:update) + +## Running BP in LiteX + +cd $LITEX/litex/tools # the folder where litex simulator resides + +./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP --threads 4 --opt-level=O0 --trace --trace-start 0 + +#The above command will generate a dut.vcd file under build/BP/gateware folder. gtkwave works fine with the generated dut.vcd. + +## Additional Information + +The BlackParrot resides in $BP/pre-alpha-release/ + +core.py in $BP folder is the wrapper that integrates BP into LiteX. + +flist.verilator in $BP is all the files that litex_sim fetches for simulation. + +The top module is $BP_FPGA_DIR/ExampleBlackParrotSystem.v + +The transducer for wishbone communication is $BP_FPGA_DIR/bp2wb_convertor.v + +if args.sdram_init is not None: #instead of ram_init for sdram init boot + soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000) diff --git a/litex/soc/cores/cpu/blackparrot/README.md b/litex/soc/cores/cpu/blackparrot/README.md index 95b10a1c..4fe921f7 100644 --- a/litex/soc/cores/cpu/blackparrot/README.md +++ b/litex/soc/cores/cpu/blackparrot/README.md @@ -1,22 +1,60 @@ -TODO: Edit +# BlackParrot in LiteX + + +## Getting Started + +TODO: modify getting started [Getting Started (Full)](GETTING_STARTED.md) + +### Prerequisites + +``` +BP sources (https://github.com/litex-hub/pythondata-cpu-blackparrot) +RISC-V toolchain built for IA architecture (prebuilt binaries provided by LiteX works fine) +Verilator (tested with Verilator 4.031) +``` + +### Installing + +``` +https://github.com/litex-hub/pythondata-cpu-blackparrot is required to run BP in LiteX. source ./setEnvironment.sh #should be sourced each time you open a terminal or just add this line to bashrc -Add $BP_TOP/external/bin to $PATH for verilator and riscv-gnu tools -Currently, we could simulate the LITEX-BIOS on BP processor. +``` + +## Running BIOS + +### Simulation +``` +cd $LITEX/litex/tools +./litex_sim.py --cpu-type blackparrot --cpu-variant standard --output-dir build/BP_Trial +``` +[![asciicast](https://asciinema.org/a/326077.svg)](https://asciinema.org/a/326077) + +### FPGA +``` +Coming soon! +``` + +## Running Linux + +### Simulation +``` +Modify litex_sim.py by replacing soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) with soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000) -#TODO Running BIOS +./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP_newversion_linux_ram/ --threads 4 --ram-init build/tests/boot.bin.uart.simu.trial +TODO: add prebuilt bbl files into python-data repository +``` -#TODO Running Linux +### FPGA +``` +Coming soon! +``` -#TODO Running on FPGA -#TODO -RISCV tool chain explanation (we currently support IA extension) -[![asciicast](https://asciinema.org/a/286568.svg)](https://asciinema.org/a/286568) diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v deleted file mode 100644 index 3c053f21..00000000 --- a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v +++ /dev/null @@ -1,356 +0,0 @@ -/** - * - * ExampleBlackParrotSystem.v - * - */ - -`include "bsg_noc_links.vh" - -module ExampleBlackParrotSystem - import bp_common_pkg::*; - import bp_common_aviary_pkg::*; - import bp_be_pkg::*; - import bp_common_rv64_pkg::*; - import bp_cce_pkg::*; - import bp_me_pkg::*; - import bp_common_cfg_link_pkg::*; - import bsg_noc_pkg::*; - #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg - `declare_bp_proc_params(bp_params_p) - `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p) - - // Tracing parameters - , parameter calc_trace_p = 0 - , parameter cce_trace_p = 0 - , parameter cmt_trace_p = 0 - , parameter dram_trace_p = 0 - , parameter npc_trace_p = 0 - , parameter dcache_trace_p = 0 - , parameter vm_trace_p = 0 - , parameter preload_mem_p = 1 - , parameter load_nbf_p = 0 - , parameter skip_init_p = 0 - , parameter cosim_p = 0 - , parameter cosim_cfg_file_p = "prog.cfg" - - , parameter mem_zero_p = 1 - , parameter mem_file_p = "prog.mem" - , parameter mem_cap_in_bytes_p = 2**25 - , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000) - - // Number of elements in the fake BlackParrot memory - , parameter use_max_latency_p = 1 - , parameter use_random_latency_p = 0 - , parameter use_dramsim2_latency_p = 0 - - , parameter max_latency_p = 15 - - , parameter dram_clock_period_in_ps_p = 1000 - , parameter dram_cfg_p = "dram_ch.ini" - , parameter dram_sys_cfg_p = "dram_sys.ini" - , parameter dram_capacity_p = 16384 - ) - (input clk_i - , input reset_i - //Wishbone interface - , input [63:0] wbm_dat_i - , output [63:0] wbm_dat_o - , input wbm_ack_i - , input wbm_err_i -// , input wbm_rty_i - , output [36:0] wbm_adr_o //TODO parametrize this - , output wbm_stb_o - , output wbm_cyc_o - , output [7:0] wbm_sel_o //TODO: how many bits ? check - , output wbm_we_o - , output [2:0] wbm_cti_o //TODO: - , output [1:0] wbm_bte_o - // , input [3:0] interrupts - ); - -`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p) - -bp_cce_mem_msg_s proc_mem_cmd_lo; -logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li; -bp_cce_mem_msg_s proc_mem_resp_li; -logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo; - -bp_cce_mem_msg_s proc_io_cmd_lo; -logic proc_io_cmd_v_lo, proc_io_cmd_ready_li; -bp_cce_mem_msg_s proc_io_resp_li; -logic proc_io_resp_v_li, proc_io_resp_yumi_lo; - -bp_cce_mem_msg_s io_cmd_lo; -logic io_cmd_v_lo, io_cmd_ready_li; -bp_cce_mem_msg_s io_resp_li; -logic io_resp_v_li, io_resp_yumi_lo; -bp_softcore - #(.bp_params_p(bp_params_p)) - softcore - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.io_cmd_o(proc_io_cmd_lo) - ,.io_cmd_v_o(proc_io_cmd_v_lo) - ,.io_cmd_ready_i(proc_io_cmd_ready_li) - - ,.io_resp_i(proc_io_resp_li) - ,.io_resp_v_i(proc_io_resp_v_li) - ,.io_resp_yumi_o(proc_io_resp_yumi_lo) - - ,.mem_cmd_o(proc_mem_cmd_lo) - ,.mem_cmd_v_o(proc_mem_cmd_v_lo) - ,.mem_cmd_ready_i(proc_mem_cmd_ready_li) - - ,.mem_resp_i(proc_mem_resp_li) - ,.mem_resp_v_i(proc_mem_resp_v_li) - ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo) - ); - - bp2wb_convertor - #(.bp_params_p(bp_params_p)) - bp2wb - (.clk_i(clk_i) - ,.reset_i(reset_i) - ,.mem_cmd_i(proc_mem_cmd_lo) - ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li) - ,.mem_cmd_ready_o(proc_mem_cmd_ready_li) - - ,.mem_resp_o(proc_mem_resp_li) - ,.mem_resp_v_o(proc_mem_resp_v_li) - ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo) - - ,.dat_i(wbm_dat_i) - ,.dat_o(wbm_dat_o) - ,.ack_i(wbm_ack_i) - ,.adr_o(wbm_adr_o) - ,.stb_o(wbm_stb_o) - ,.cyc_o(wbm_cyc_o) - ,.sel_o(wbm_sel_o ) - ,.we_o(wbm_we_o) - ,.cti_o(wbm_cti_o) - ,.bte_o(wbm_bte_o ) - // ,.rty_i(wbm_rty_i) - ,.err_i(wbm_err_i) - ); - -/* -bp_mem - mem - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.mem_cmd_i(proc_mem_cmd_lo) - ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li) - ,.mem_cmd_ready_o(proc_mem_cmd_ready_li) - - ,.mem_resp_o(proc_mem_resp_li) - ,.mem_resp_v_o(proc_mem_resp_v_li) - ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo) - ); -*/ -logic program_finish_lo; -bp_nonsynth_host - #(.bp_params_p(bp_params_p)) - host - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.io_cmd_i(proc_io_cmd_lo) - ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li) - ,.io_cmd_ready_o(proc_io_cmd_ready_li) - - ,.io_resp_o(proc_io_resp_li) - ,.io_resp_v_o(proc_io_resp_v_li) - ,.io_resp_yumi_i(proc_io_resp_yumi_lo) - - ,.program_finish_o(program_finish_lo) - ); - -/*bind bp_be_top - bp_nonsynth_commit_tracer - #(.bp_params_p(bp_params_p)) - commit_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i('0) - - ,.commit_v_i(be_calculator.commit_pkt.instret) - ,.commit_pc_i(be_calculator.commit_pkt.pc) - ,.commit_instr_i(be_calculator.commit_pkt.instr) - - ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v) - ,.rd_addr_i(be_calculator.wb_pkt.rd_addr) - ,.rd_data_i(be_calculator.wb_pkt.rd_data) - ); -*/ -/* bind bp_be_top - bp_nonsynth_cosim - #(.bp_params_p(bp_params_p)) - cosim - (.clk_i(clk_i) - ,.reset_i(reset_i) - ,.en_i(ExampleBlackParrotSystem.cosim_p == 1) - - ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id) - // Want to pass config file as a parameter, but cannot in Verilator 4.025 - // Parameter-resolved constants must not use dotted references - ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p) - - ,.commit_v_i(be_calculator.commit_pkt.instret) - ,.commit_pc_i(be_calculator.commit_pkt.pc) - ,.commit_instr_i(be_calculator.commit_pkt.instr) - - ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v) - ,.rd_addr_i(be_calculator.wb_pkt.rd_addr) - ,.rd_data_i(be_calculator.wb_pkt.rd_data) - - ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt) - ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause) - ); -*/ -/*bind bp_be_top - bp_be_nonsynth_perf - #(.bp_params_p(bp_params_p)) - perf - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id) - - ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v) - ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v) - ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v) - ,.poison_i(be_calculator.exc_stage_r[2].poison_v) - ,.roll_i(be_calculator.exc_stage_r[2].roll_v) - - ,.instr_cmt_i(be_calculator.commit_pkt.instret) - - ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo) - ); -*/ - /* bind bp_be_director - bp_be_nonsynth_npc_tracer - #(.bp_params_p(bp_params_p)) - npc_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id) - - ,.npc_w_v(npc_w_v) - ,.npc_n(npc_n) - ,.npc_r(npc_r) - ,.expected_npc_o(expected_npc_o) - - ,.fe_cmd_i(fe_cmd) - ,.fe_cmd_v(fe_cmd_v) - - ,.commit_pkt_i(commit_pkt) - ); -*/ - /*bind bp_be_dcache - bp_be_nonsynth_dcache_tracer - #(.bp_params_p(bp_params_p)) - dcache_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i(cfg_bus_cast_i.core_id) - - ,.v_tv_r(v_tv_r) - //,.cache_miss_i(cache_miss_i) - - ,.paddr_tv_r(paddr_tv_r) - ,.uncached_tv_r(uncached_tv_r) - ,.load_op_tv_r(load_op_tv_r) - ,.store_op_tv_r(store_op_tv_r) - ,.lr_op_tv_r(lr_op_tv_r) - ,.sc_op_tv_r(sc_op_tv_r) - ,.store_data(data_tv_r) - ,.load_data(data_o) - );*/ -/* - bind bp_be_top - bp_be_nonsynth_calc_tracer - #(.bp_params_p(bp_params_p)) - calc_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id) - - ,.issue_pkt_i(be_checker.scheduler.issue_pkt) - ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o) - - ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v) - ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v) - ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v) - ,.dispatch_pkt_i(be_calculator.dispatch_pkt) - - ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc) - ,.ex1_btaken_i(be_calculator.pipe_int.btaken) - ,.iwb_result_i(be_calculator.comp_stage_n[3]) - ,.fwb_result_i(be_calculator.comp_stage_n[4]) - - ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5]) - - ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception) - ,.mtvec_i(be_mem.csr.mtvec_n) - ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p]) - ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret) - ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p]) - ,.mcause_i(be_mem.csr.mcause_n) - - ,.priv_mode_i(be_mem.csr.priv_mode_n) - ,.mpp_i(be_mem.csr.mstatus_n.mpp) - ); - - bind bp_core_minimal - bp_be_nonsynth_vm_tracer - #(.bp_params_p(bp_params_p)) - vm_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id) - - ,.itlb_clear_i(fe.mem.itlb.flush_i) - ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i) - ,.itlb_vtag_i(fe.mem.itlb.vtag_i) - ,.itlb_entry_i(fe.mem.itlb.entry_i) - - ,.dtlb_clear_i(be.be_mem.dtlb.flush_i) - ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i) - ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i) - ,.dtlb_entry_i(be.be_mem.dtlb.entry_i) - ); -*/ - /*bp_mem_nonsynth_tracer - #(.bp_params_p(bp_params_p)) - bp_mem_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1)) - ,.reset_i(reset_i) - - ,.mem_cmd_i(proc_mem_cmd_lo) - ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li) - ,.mem_cmd_ready_i(proc_mem_cmd_ready_li) - - ,.mem_resp_i(proc_mem_resp_li) - ,.mem_resp_v_i(proc_mem_resp_v_li) - ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo) - ); -*/ -/*bp_nonsynth_if_verif - #(.bp_params_p(bp_params_p)) - if_verif - (); -*/ -endmodule - diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v deleted file mode 100644 index c226c331..00000000 --- a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v +++ /dev/null @@ -1,357 +0,0 @@ -/** - * - * ExampleBlackParrotSystem.v - * - */ - -`include "bsg_noc_links.vh" - -module ExampleBlackParrotSystem - import bp_common_pkg::*; - import bp_common_aviary_pkg::*; - import bp_be_pkg::*; - import bp_common_rv64_pkg::*; - import bp_cce_pkg::*; - import bp_me_pkg::*; - import bp_common_cfg_link_pkg::*; - import bsg_noc_pkg::*; - #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg - `declare_bp_proc_params(bp_params_p) - `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p) - - // Tracing parameters - , parameter calc_trace_p = 0 - , parameter cce_trace_p = 0 - , parameter cmt_trace_p = 1 - , parameter dram_trace_p = 1 - , parameter npc_trace_p = 0 - , parameter dcache_trace_p = 0 - , parameter vm_trace_p = 0 - , parameter preload_mem_p = 1 - , parameter load_nbf_p = 0 - , parameter skip_init_p = 0 - , parameter cosim_p = 0 - , parameter cosim_cfg_file_p = "prog.cfg" - - , parameter mem_zero_p = 1 - , parameter mem_file_p = "prog.mem" - , parameter mem_cap_in_bytes_p = 2**25 - , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000) - - // Number of elements in the fake BlackParrot memory - , parameter use_max_latency_p = 1 - , parameter use_random_latency_p = 0 - , parameter use_dramsim2_latency_p = 0 - - , parameter max_latency_p = 15 - - , parameter dram_clock_period_in_ps_p = 1000 - , parameter dram_cfg_p = "dram_ch.ini" - , parameter dram_sys_cfg_p = "dram_sys.ini" - , parameter dram_capacity_p = 16384 - ) - (input clk_i - , input reset_i - //Wishbone interface - , input [63:0] wbm_dat_i - , output [63:0] wbm_dat_o - , input wbm_ack_i - , input wbm_err_i -// , input wbm_rty_i - , output [36:0] wbm_adr_o //TODO parametrize this - , output wbm_stb_o - , output wbm_cyc_o - , output [7:0] wbm_sel_o //TODO: how many bits ? check - , output wbm_we_o - , output [2:0] wbm_cti_o //TODO: - , output [1:0] wbm_bte_o - // , input [3:0] interrupts - ); - -`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p) - -bp_cce_mem_msg_s proc_mem_cmd_lo; -logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li; -bp_cce_mem_msg_s proc_mem_resp_li; -logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo; - -bp_cce_mem_msg_s proc_io_cmd_lo; -logic proc_io_cmd_v_lo, proc_io_cmd_ready_li; -bp_cce_mem_msg_s proc_io_resp_li; -logic proc_io_resp_v_li, proc_io_resp_yumi_lo; - -bp_cce_mem_msg_s io_cmd_lo; -logic io_cmd_v_lo, io_cmd_ready_li; -bp_cce_mem_msg_s io_resp_li; -logic io_resp_v_li, io_resp_yumi_lo; -bp_softcore - #(.bp_params_p(bp_params_p)) - softcore - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.io_cmd_o(proc_io_cmd_lo) - ,.io_cmd_v_o(proc_io_cmd_v_lo) - ,.io_cmd_ready_i(proc_io_cmd_ready_li) - - ,.io_resp_i(proc_io_resp_li) - ,.io_resp_v_i(proc_io_resp_v_li) - ,.io_resp_yumi_o(proc_io_resp_yumi_lo) - - ,.mem_cmd_o(proc_mem_cmd_lo) - ,.mem_cmd_v_o(proc_mem_cmd_v_lo) - ,.mem_cmd_ready_i(proc_mem_cmd_ready_li) - - ,.mem_resp_i(proc_mem_resp_li) - ,.mem_resp_v_i(proc_mem_resp_v_li) - ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo) - ); - - bp2wb_convertor - #(.bp_params_p(bp_params_p)) - bp2wb - (.clk_i(clk_i) - ,.reset_i(reset_i) - ,.mem_cmd_i(proc_mem_cmd_lo) - ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li) - ,.mem_cmd_ready_o(proc_mem_cmd_ready_li) - - ,.mem_resp_o(proc_mem_resp_li) - ,.mem_resp_v_o(proc_mem_resp_v_li) - ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo) - - ,.dat_i(wbm_dat_i) - ,.dat_o(wbm_dat_o) - ,.ack_i(wbm_ack_i) - ,.adr_o(wbm_adr_o) - ,.stb_o(wbm_stb_o) - ,.cyc_o(wbm_cyc_o) - ,.sel_o(wbm_sel_o ) - ,.we_o(wbm_we_o) - ,.cti_o(wbm_cti_o) - ,.bte_o(wbm_bte_o ) - // ,.rty_i(wbm_rty_i) - ,.err_i(wbm_err_i) - ); - -/* -bp_mem - mem - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.mem_cmd_i(proc_mem_cmd_lo) - ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li) - ,.mem_cmd_ready_o(proc_mem_cmd_ready_li) - - ,.mem_resp_o(proc_mem_resp_li) - ,.mem_resp_v_o(proc_mem_resp_v_li) - ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo) - ); -*/ -logic program_finish_lo; -assign proc_io_cmd_ready_li = 1; -/*bp_nonsynth_host - #(.bp_params_p(bp_params_p)) - host - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.io_cmd_i(proc_io_cmd_lo) - ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li) - ,.io_cmd_ready_o(proc_io_cmd_ready_li) - - ,.io_resp_o(proc_io_resp_li) - ,.io_resp_v_o(proc_io_resp_v_li) - ,.io_resp_yumi_i(proc_io_resp_yumi_lo) - - ,.program_finish_o(program_finish_lo) - ); -*/ -bind bp_be_top - bp_nonsynth_commit_tracer - #(.bp_params_p(bp_params_p)) - commit_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i('0) - - ,.commit_v_i(be_calculator.commit_pkt.instret) - ,.commit_pc_i(be_calculator.commit_pkt.pc) - ,.commit_instr_i(be_calculator.commit_pkt.instr) - - ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v) - ,.rd_addr_i(be_calculator.wb_pkt.rd_addr) - ,.rd_data_i(be_calculator.wb_pkt.rd_data) - ); - -/* bind bp_be_top - bp_nonsynth_cosim - #(.bp_params_p(bp_params_p)) - cosim - (.clk_i(clk_i) - ,.reset_i(reset_i) - ,.en_i(ExampleBlackParrotSystem.cosim_p == 1) - - ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id) - // Want to pass config file as a parameter, but cannot in Verilator 4.025 - // Parameter-resolved constants must not use dotted references - ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p) - - ,.commit_v_i(be_calculator.commit_pkt.instret) - ,.commit_pc_i(be_calculator.commit_pkt.pc) - ,.commit_instr_i(be_calculator.commit_pkt.instr) - - ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v) - ,.rd_addr_i(be_calculator.wb_pkt.rd_addr) - ,.rd_data_i(be_calculator.wb_pkt.rd_data) - - ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt) - ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause) - ); -*/ -/*bind bp_be_top - bp_be_nonsynth_perf - #(.bp_params_p(bp_params_p)) - perf - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id) - - ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v) - ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v) - ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v) - ,.poison_i(be_calculator.exc_stage_r[2].poison_v) - ,.roll_i(be_calculator.exc_stage_r[2].roll_v) - - ,.instr_cmt_i(be_calculator.commit_pkt.instret) - - ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo) - ); -*/ - /* bind bp_be_director - bp_be_nonsynth_npc_tracer - #(.bp_params_p(bp_params_p)) - npc_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id) - - ,.npc_w_v(npc_w_v) - ,.npc_n(npc_n) - ,.npc_r(npc_r) - ,.expected_npc_o(expected_npc_o) - - ,.fe_cmd_i(fe_cmd) - ,.fe_cmd_v(fe_cmd_v) - - ,.commit_pkt_i(commit_pkt) - ); -*/ - /*bind bp_be_dcache - bp_be_nonsynth_dcache_tracer - #(.bp_params_p(bp_params_p)) - dcache_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i(cfg_bus_cast_i.core_id) - - ,.v_tv_r(v_tv_r) - //,.cache_miss_i(cache_miss_i) - - ,.paddr_tv_r(paddr_tv_r) - ,.uncached_tv_r(uncached_tv_r) - ,.load_op_tv_r(load_op_tv_r) - ,.store_op_tv_r(store_op_tv_r) - ,.lr_op_tv_r(lr_op_tv_r) - ,.sc_op_tv_r(sc_op_tv_r) - ,.store_data(data_tv_r) - ,.load_data(data_o) - );*/ -/* - bind bp_be_top - bp_be_nonsynth_calc_tracer - #(.bp_params_p(bp_params_p)) - calc_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id) - - ,.issue_pkt_i(be_checker.scheduler.issue_pkt) - ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o) - - ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v) - ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v) - ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v) - ,.dispatch_pkt_i(be_calculator.dispatch_pkt) - - ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc) - ,.ex1_btaken_i(be_calculator.pipe_int.btaken) - ,.iwb_result_i(be_calculator.comp_stage_n[3]) - ,.fwb_result_i(be_calculator.comp_stage_n[4]) - - ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5]) - - ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception) - ,.mtvec_i(be_mem.csr.mtvec_n) - ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p]) - ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret) - ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p]) - ,.mcause_i(be_mem.csr.mcause_n) - - ,.priv_mode_i(be_mem.csr.priv_mode_n) - ,.mpp_i(be_mem.csr.mstatus_n.mpp) - ); - - bind bp_core_minimal - bp_be_nonsynth_vm_tracer - #(.bp_params_p(bp_params_p)) - vm_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1)) - ,.reset_i(reset_i) - ,.freeze_i('0) - - ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id) - - ,.itlb_clear_i(fe.mem.itlb.flush_i) - ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i) - ,.itlb_vtag_i(fe.mem.itlb.vtag_i) - ,.itlb_entry_i(fe.mem.itlb.entry_i) - - ,.dtlb_clear_i(be.be_mem.dtlb.flush_i) - ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i) - ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i) - ,.dtlb_entry_i(be.be_mem.dtlb.entry_i) - ); -*/ -/* bp_mem_nonsynth_tracer - #(.bp_params_p(bp_params_p)) - bp_mem_tracer - (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1)) - ,.reset_i(reset_i) - - ,.mem_cmd_i(proc_mem_cmd_lo) - ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li) - ,.mem_cmd_ready_i(proc_mem_cmd_ready_li) - - ,.mem_resp_i(proc_mem_resp_li) - ,.mem_resp_v_i(proc_mem_resp_v_li) - ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo) - ); -*/ -/*bp_nonsynth_if_verif - #(.bp_params_p(bp_params_p)) - if_verif - (); -*/ -endmodule - diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v deleted file mode 100644 index 90ed0854..00000000 --- a/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v +++ /dev/null @@ -1,267 +0,0 @@ -/** - * bp2wb_convertor.v - * DESCRIPTION: THIS MODULE ADAPTS BP MEMORY BUS TO 64-BIT WISHBONE - */ - -module bp2wb_convertor - import bp_common_pkg::*; - import bp_common_aviary_pkg::*; - import bp_cce_pkg::*; - import bp_me_pkg::*; - #(parameter bp_params_e bp_params_p = e_bp_single_core_cfg - `declare_bp_proc_params(bp_params_p) - `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p) - -// , parameter [paddr_width_p-1:0] dram_offset_p = '0 - , localparam num_block_words_lp = cce_block_width_p / 64 - , localparam num_block_bytes_lp = cce_block_width_p / 8 - , localparam num_word_bytes_lp = dword_width_p / 8 - , localparam block_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_bytes_lp) - , localparam word_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_words_lp) - , localparam byte_offset_bits_lp = `BSG_SAFE_CLOG2(num_word_bytes_lp) - , localparam wbone_data_width = 64 - , localparam wbone_addr_ubound = paddr_width_p - , localparam mem_granularity = 64 //TODO: adapt selection bit parametrized - , localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity - , localparam total_datafetch_cycle_lp = cce_block_width_p / wbone_data_width - , localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp) - , localparam cached_addr_base = 32'h7000_0000//6000_0000 //32'h4000_4000// - ) - ( input clk_i - ,(* mark_debug = "true" *) input reset_i - - // BP side - ,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0] mem_cmd_i - ,(* mark_debug = "true" *) input mem_cmd_v_i - ,(* mark_debug = "true" *) output mem_cmd_ready_o - - , output [cce_mem_msg_width_lp-1:0] mem_resp_o - , (* mark_debug = "true" *) output mem_resp_v_o - , (* mark_debug = "true" *) input mem_resp_yumi_i - - // Wishbone side - , (* mark_debug = "true" *) input [63:0] dat_i - , (* mark_debug = "true" *) output logic [63:0] dat_o - , (* mark_debug = "true" *) input ack_i - , input err_i -// , input rty_i - , (* mark_debug = "true" *) output logic [wbone_addr_ubound-wbone_addr_lbound-1:0] adr_o//TODO: Double check!!! - , (* mark_debug = "true" *) output logic stb_o - , output cyc_o - , output [7:0] sel_o //TODO: double check!!! - , (* mark_debug = "true" *) output we_o - , output [2:0] cti_o //TODO: hardwire in Litex - , output [1:0] bte_o //TODO: hardwire in Litex - - ); - - `declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p); - - //locals - (* mark_debug = "true" *) logic [total_datafetch_cycle_width:0] ack_ctr = 0; - (* mark_debug = "true" *) bp_cce_mem_msg_s mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_debug;//, mem_cmd_debug2 - (* mark_debug = "true" *) logic ready_li, v_li, stb_justgotack; - (* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_lo; - (* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_li; - (* mark_debug = "true" *) wire [paddr_width_p-1:0] mem_cmd_addr_l; - (* mark_debug = "true" *) logic set_stb; - - - //Handshaking between Wishbone and BlackParrot through convertor - //3.1.3:At every rising edge of [CLK_I] the terminating signal(ACK) is sampled. If it - //is asserted, then [STB_O] is negated. - - assign ready_li = ( ack_ctr == 0 ) & !set_stb & !mem_resp_v_o; - assign mem_cmd_ready_o = ready_li;//!stb_o then ready to take! - // assign v_li = (ack_ctr == total_datafetch_cycle_lp-1); - assign mem_resp_v_o = v_li; - assign stb_o = (set_stb) && !stb_justgotack; - assign cyc_o = stb_o; - assign sel_o = 8'b11111111; - assign cti_o = 0; - assign bte_o = 0; - - initial begin - ack_ctr = 0; - end - - -//Flip stb after each ack--->RULE 3.20: -// Every time we get an ACK from WB, increment counter until the counter reaches to total_datafetch_cycle_lp - always_ff @(posedge clk_i) - begin - - if(reset_i) - begin - ack_ctr <= 0; - set_stb <= 0; - v_li <=0; - end - else if (v_li) - begin - if (mem_resp_yumi_i) - begin - v_li <= 0; - ack_ctr <= 0; - end - end - else if (mem_cmd_v_i) - begin - //data_li <= 0; - set_stb <= 1; - v_li <= 0; - stb_justgotack <= 0; - end - - else - begin - if (ack_i)//stb should be negated after ack - begin - stb_justgotack <= 1; - data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= dat_i; - if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.header.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine - begin - v_li <=1; - set_stb <= 0; - end - else - ack_ctr <= ack_ctr + 1; - end - else - begin - stb_justgotack <= 0; - v_li <=0; - end - end - end - - //Packet Pass from BP to BP2WB - assign mem_cmd_cast_i = mem_cmd_i; - bp_cce_mem_msg_s mem_cmd_r; - bsg_dff_reset_en - #(.width_p(cce_mem_msg_width_lp)) - mshr_reg - (.clk_i(clk_i) - ,.reset_i(reset_i) - ,.en_i(mem_cmd_v_i)//when - ,.data_i(mem_cmd_i) - ,.data_o(mem_cmd_r) - ); - - //Addr && Data && Command Pass from BP2WB to WB - logic [wbone_addr_lbound-1:0] throw_away; - assign mem_cmd_addr_l = mem_cmd_r.header.addr; - assign data_lo = mem_cmd_r.data; - logic [39:0] mem_cmd_addr_l_zero64; - always_comb begin - if( mem_cmd_addr_l < cached_addr_base ) - begin - adr_o = mem_cmd_addr_l[wbone_addr_ubound-1:wbone_addr_lbound];//no need to change address for uncached stores/loads - dat_o = data_lo[(0*wbone_data_width) +: wbone_data_width];//unchached data is stored in LS 64bits - end - - else - begin - mem_cmd_addr_l_zero64 = mem_cmd_addr_l >> 6 << 6; - {adr_o,throw_away} = mem_cmd_addr_l_zero64 + (ack_ctr*8);//TODO:careful - dat_o = data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width]; - end - end - - assign we_o = (mem_cmd_r.header.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wb}); - -//Data Pass from BP2WB to BP - -wire [cce_block_width_p-1:0] rd_word_offset = mem_cmd_r.header.addr[3+:3]; -//wire [cce_block_width_p-1:0] rd_byte_offset = mem_cmd_r.addr[0+:3]; -wire [cce_block_width_p-1:0] rd_bit_shift = rd_word_offset*64; // We rely on receiver to adjust bits - -(* mark_debug = "true" *) wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.header.msg_type == e_cce_mem_uc_rd) - ? data_li >> rd_bit_shift - : data_li; - - - -assign mem_resp_cast_o = '{data : data_li_resp - ,header :'{payload : mem_cmd_r.header.payload - ,size : mem_cmd_r.header.size - ,addr : mem_cmd_r.header.addr - ,msg_type: mem_cmd_r.header.msg_type - } - }; - -assign mem_resp_o = mem_resp_cast_o; - -/*********************************************/ -/*DEBUG SECTION*/ - -/* always_comb - begin - if (mem_cmd_yumi_o == 1)// && mem_cmd_addr_l >=32'h8000_0000) - begin - mem_cmd_debug = mem_cmd_i; - if(mem_cmd_debug.addr >= 32'h80000000) - begin - $display("myarray == %x", mem_cmd_debug.addr); - $display("myarray == %x", mem_cmd_debug.msg_type); - if(mem_cmd_debug.msg_type>=3) - $display("myarray == %x", mem_cmd_debug.data); - - end - end - end - -always_comb -begin - if(mem_resp_v_o) - begin - mem_cmd_debug2 = mem_resp_o; - if(mem_cmd_debug2.addr >= 32'h80000000) - begin - $display("myresp == %x", mem_cmd_debug2.addr); - $display("myresp == %x", mem_cmd_debug2.msg_type); - if(mem_cmd_debug2.msg_type<=1) - $display("myresp == %x", mem_cmd_debug2.data); - end - end -end -*/ - -/*wire [3:0] fake_msg_type; -wire [10:0] fake_payload; -wire [2:0] fake_size; -wire [39:0] fake_addr; -assign fake_payload = mem_cmd_r.header.payload; -assign fake_size = mem_cmd_r.header.size; -assign fake_addr = mem_cmd_r.header.addr; -assign fake_msg_type = mem_cmd_r.header.msg_type; -*/ -(* mark_debug = "true" *) logic debug_wire; - initial begin - debug_wire = 0; - end - - assign mem_cmd_debug = mem_cmd_i; - -always_ff @(posedge clk_i) -debug_wire <= (ack_i && mem_cmd_debug.header.addr >= 32'h80000000); - -/* always_ff @(posedge clk_i) - begin - if(mem_cmd_v_i && mem_cmd_debug.header.addr >= 32'h80000000) - begin - debug_wire <= 1; - // $display("addr == %x", mem_cmd_debug.header.addr); - end*/ -/* if (mem_resp_v_o && debug_ctr < 64 && mem_cmd_debug.header.addr >= 32'h80000000) - begin - debug_gotdata[((debug_ctr-1)*512) +: 512] <= data_li_resp; - $display("data == %x", data_li_resp); - end*/ -// end - -wire [3:0] typean; -assign typean = mem_cmd_r.header.msg_type; - -endmodule - diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v deleted file mode 100644 index a6fdae9a..00000000 --- a/litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v +++ /dev/null @@ -1,55 +0,0 @@ -/* -* bsg_mem_1rw_sync_mask_write_bit.v -* -* distributed synchronous 1-port ram for xilinx ultrascale or ultrascale plus FPGA -* Write mode: No-change | Read mode: No-change -* Note: -* There are 2 basic BRAM library primitives, RAMB18E2 and RAMB36E2 in Vivado. -* But none of them support bit-wise mask. They have Byte-wide write enable ports though. -* So we use the RAM_STYLE attribute to instruct the tool to infer distributed LUT RAM instead. -* -* To save resources, the code is written to be inferred as Signle-port distributed ram RAM64X1S. -* https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf -* -*/ - - -module bsg_mem_1rw_sync_mask_write_bit #( - parameter width_p = "inv" - , parameter els_p = "inv" - , parameter latch_last_read_p=0 - , parameter enable_clock_gating_p=0 - , localparam addr_width_lp = `BSG_SAFE_CLOG2(els_p) -) ( - input clk_i - , input reset_i - , input [ width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [ width_p-1:0] w_mask_i - , input w_i - , output [ width_p-1:0] data_o -); - - wire unused = reset_i; - - (* ram_style = "distributed" *) logic [width_p-1:0] mem [els_p-1:0]; - - logic [width_p-1:0] data_r; - always_ff @(posedge clk_i) begin - if (v_i & ~w_i) - data_r <= mem[addr_i]; - end - - assign data_o = data_r; - - for (genvar i=0; i> 1'b1; - - always_comb - begin - mem_cmd_v_o = cfg_v_lo; - - // uncached store - mem_cmd_cast_o.msg_type = e_cce_mem_uc_wr; - mem_cmd_cast_o.addr = bp_cfg_base_addr_gp; - mem_cmd_cast_o.payload = '0; - mem_cmd_cast_o.size = e_mem_size_8; - mem_cmd_cast_o.data = cce_block_width_p'({cfg_core_lo, cfg_addr_lo, cfg_data_lo}); - end - - always_comb - begin - ucode_cnt_clr = 1'b0; - ucode_cnt_inc = 1'b0; - - cfg_v_lo = '0; - cfg_core_lo = 8'hff; - cfg_addr_lo = '0; - cfg_data_lo = '0; - - case (state_r) - RESET: begin - state_n = skip_ram_init_p ? BP_FREEZE_CLR : BP_RESET_SET; - - ucode_cnt_clr = 1'b1; - end - BP_RESET_SET: begin - state_n = BP_FREEZE_SET; - - cfg_v_lo = 1'b1; - cfg_addr_lo = bp_cfg_reg_reset_gp; - cfg_data_lo = cfg_data_width_p'(1); - end - BP_FREEZE_SET: begin - state_n = BP_RESET_CLR; - - cfg_v_lo = 1'b1; - cfg_addr_lo = bp_cfg_reg_freeze_gp; - cfg_data_lo = cfg_data_width_p'(1); - end - BP_RESET_CLR: begin - state_n = SEND_RAM_LO; - - cfg_v_lo = 1'b1; - cfg_addr_lo = bp_cfg_reg_reset_gp; - cfg_data_lo = cfg_data_width_p'(0); - end - SEND_RAM_LO: begin - state_n = SEND_RAM_HI; - - cfg_v_lo = 1'b1; - cfg_addr_lo = cfg_addr_width_p'(bp_cfg_mem_base_cce_ucode_gp) + (ucode_cnt_r << 1); - cfg_data_lo = cce_inst_boot_rom_data[0+:cfg_data_width_p]; - // TODO: This is nonsynth, won't work on FPGA - cfg_data_lo = (|cfg_data_lo === 'X) ? '0 : cfg_data_lo; - end - SEND_RAM_HI: begin - state_n = ucode_prog_done ? SEND_CCE_NORMAL : SEND_RAM_LO; - - ucode_cnt_inc = 1'b1; - - cfg_v_lo = 1'b1; - cfg_addr_lo = cfg_addr_width_p'(bp_cfg_mem_base_cce_ucode_gp) + (ucode_cnt_r << 1) + 1'b1; - cfg_data_lo = cfg_data_width_p'(cce_inst_boot_rom_data[inst_width_p-1:cfg_data_width_p]); - // TODO: This is nonsynth, won't work on FPGA - cfg_data_lo = (|cfg_data_lo === 'X) ? '0 : cfg_data_lo; - end - SEND_CCE_NORMAL: begin - state_n = SEND_ICACHE_NORMAL; - - cfg_v_lo = 1'b1; - cfg_addr_lo = bp_cfg_reg_cce_mode_gp; - cfg_data_lo = cfg_data_width_p'(e_cce_mode_normal); - end - SEND_ICACHE_NORMAL: begin - state_n = SEND_DCACHE_NORMAL; - - cfg_v_lo = 1'b1; - cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_icache_mode_gp); - cfg_data_lo = cfg_data_width_p'(e_dcache_lce_mode_normal); // TODO: tapeout hack, change to icache - end - SEND_DCACHE_NORMAL: begin - state_n = SEND_PC_LO; - - cfg_v_lo = 1'b1; - cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_dcache_mode_gp); - cfg_data_lo = cfg_data_width_p'(e_dcache_lce_mode_normal); - end - SEND_PC_LO: begin - state_n = SEND_PC_HI; - - cfg_v_lo = 1'b1; - cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_start_pc_lo_gp); - cfg_data_lo = bp_pc_entry_point_gp[0+:cfg_data_width_p]; - end - SEND_PC_HI: begin - state_n = BP_FREEZE_CLR; - - cfg_v_lo = 1'b1; - cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_start_pc_hi_gp); - cfg_data_lo = cfg_data_width_p'(bp_pc_entry_point_gp[vaddr_width_p-1:cfg_data_width_p]); - end - BP_FREEZE_CLR: begin - state_n = DONE; - - cfg_v_lo = 1'b1; - cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_freeze_gp); - cfg_data_lo = cfg_data_width_p'(0);; - end - DONE: begin - state_n = DONE; - end - default: begin - state_n = RESET; - end - endcase - end - -endmodule diff --git a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_common_pkg.vh b/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_common_pkg.vh deleted file mode 100644 index 9500673b..00000000 --- a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_common_pkg.vh +++ /dev/null @@ -1,55 +0,0 @@ -/* - * bp_common_pkg.vh - * - * Contains the interface structures used for communicating between FE, BE, ME in BlackParrot. - * Additionally contains global parameters used to configure the system. In the future, when - * multiple configurations are supported, these global parameters will belong to groups - * e.g. SV39, VM-disabled, ... - * - */ - -package bp_common_pkg; - - `include "bsg_defines.v" - `include "bp_common_defines.vh" - `include "bp_common_fe_be_if.vh" - `include "bp_common_me_if.vh" - - /* - * RV64 specifies a 64b effective address and 32b instruction. - * BlackParrot supports SV39 virtual memory, which specifies 39b virtual / 56b physical address. - * Effective addresses must have bits 39-63 match bit 38 - * or a page fault exception will occur during translation. - * Currently, we only support a very limited number of parameter configurations. - * Thought: We could have a `define surrounding core instantiations of each parameter and then - * when they import this package, `declare the if structs. No more casting! - */ - - localparam bp_eaddr_width_gp = 64; - localparam bp_instr_width_gp = 32; - - parameter bp_sv39_page_table_depth_gp = 3; - parameter bp_sv39_pte_width_gp = 64; - parameter bp_sv39_vaddr_width_gp = 39; - parameter bp_sv39_paddr_width_gp = 56; - parameter bp_sv39_ppn_width_gp = 44; - parameter bp_page_size_in_bytes_gp = 4096; - parameter bp_page_offset_width_gp = `BSG_SAFE_CLOG2(bp_page_size_in_bytes_gp); - - parameter bp_data_resp_num_flit_gp = 4; - parameter bp_data_cmd_num_flit_gp = 4; - - localparam dram_base_addr_gp = 32'h5000_0000; - - localparam cfg_link_dev_base_addr_gp = 32'h01??_????; - localparam clint_dev_base_addr_gp = 32'h02??_????; - localparam host_dev_base_addr_gp = 32'h03??_????; - localparam plic_dev_base_addr_gp = 32'h0c??_????; - - localparam mipi_reg_base_addr_gp = 32'h0200_0???; - localparam mtimecmp_reg_base_addr_gp = 32'h0200_4???; - localparam mtime_reg_addr_gp = 32'h0200_bff8; - localparam plic_reg_base_addr_gp = 32'h0c00_0???; - -endpackage : bp_common_pkg - diff --git a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_nonsynth_host.v b/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_nonsynth_host.v deleted file mode 100644 index e64ce690..00000000 --- a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_nonsynth_host.v +++ /dev/null @@ -1,190 +0,0 @@ - -module bp_nonsynth_host - import bp_common_pkg::*; - import bp_common_aviary_pkg::*; - import bp_be_pkg::*; - import bp_common_rv64_pkg::*; - import bp_cce_pkg::*; - import bsg_noc_pkg::*; - import bp_cfg_link_pkg::*; - #(parameter bp_cfg_e cfg_p = e_bp_inv_cfg - `declare_bp_proc_params(cfg_p) - `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p) - ) - (input clk_i - , input reset_i - - , input [cce_mem_msg_width_lp-1:0] mem_cmd_i - , input mem_cmd_v_i - , output logic mem_cmd_yumi_o - - , output logic [cce_mem_msg_width_lp-1:0] mem_resp_o - , output logic mem_resp_v_o - , input mem_resp_ready_i - - , output [num_core_p-1:0] program_finish_o - ,(* mark_debug = "true" *) output logic all_finished_debug_o //SC_add - , (* mark_debug = "true" *) output logic core_passed_debug - , (* mark_debug = "true" *) output logic core_failed_debug - ); - -`declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p); - -// HOST I/O mappings -//localparam host_dev_base_addr_gp = 32'h03??_????; - -// Host I/O mappings (arbitrarily decided for now) -// Overall host controls 32'h0300_0000-32'h03FF_FFFF - -localparam hprint_base_addr_gp = paddr_width_p'(32'h0300_0???); -localparam cprint_base_addr_gp = paddr_width_p'(64'h0300_1???); -localparam finish_base_addr_gp = paddr_width_p'(64'h0300_2???); - -bp_cce_mem_msg_s mem_cmd_cast_i; - -assign mem_cmd_cast_i = mem_cmd_i; - -localparam lg_num_core_lp = `BSG_SAFE_CLOG2(num_core_p); - -logic hprint_data_cmd_v; -logic cprint_data_cmd_v; -logic finish_data_cmd_v; - -always_comb - begin - hprint_data_cmd_v = 1'b0; - cprint_data_cmd_v = 1'b0; - finish_data_cmd_v = 1'b0; - - unique - casez (mem_cmd_cast_i.addr) - hprint_base_addr_gp: hprint_data_cmd_v = mem_cmd_v_i; - cprint_base_addr_gp: cprint_data_cmd_v = mem_cmd_v_i; - finish_base_addr_gp: finish_data_cmd_v = mem_cmd_v_i; - default: begin end - endcase - end - -logic [num_core_p-1:0] hprint_w_v_li; -logic [num_core_p-1:0] cprint_w_v_li; -logic [num_core_p-1:0] finish_w_v_li; - -// Memory-mapped I/O is 64 bit aligned -localparam byte_offset_width_lp = 3; -wire [lg_num_core_lp-1:0] mem_cmd_core_enc = - mem_cmd_cast_i.addr[byte_offset_width_lp+:lg_num_core_lp]; - -bsg_decode_with_v - #(.num_out_p(num_core_p)) - hprint_data_cmd_decoder - (.v_i(hprint_data_cmd_v) - ,.i(mem_cmd_core_enc) - - ,.o(hprint_w_v_li) - ); - -bsg_decode_with_v - #(.num_out_p(num_core_p)) - cprint_data_cmd_decoder - (.v_i(cprint_data_cmd_v) - ,.i(mem_cmd_core_enc) - - ,.o(cprint_w_v_li) - ); - -bsg_decode_with_v - #(.num_out_p(num_core_p)) - finish_data_cmd_decoder - (.v_i(finish_data_cmd_v) - ,.i(mem_cmd_core_enc) - - ,.o(finish_w_v_li) - ); - -logic [num_core_p-1:0] finish_r; -bsg_dff_reset - #(.width_p(num_core_p)) - finish_accumulator - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.data_i(finish_r | finish_w_v_li) - ,.data_o(finish_r) - ); - -logic all_finished_r; -bsg_dff_reset - #(.width_p(1)) - all_finished_reg - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.data_i(&finish_r) - ,.data_o(all_finished_r) - ); - -assign program_finish_o = finish_r; - -always_ff @(negedge clk_i) - begin - for (integer i = 0; i < num_core_p; i++) - begin - if (hprint_w_v_li[i] & mem_cmd_yumi_o) - $display("[CORE%0x PRT] %x", i, mem_cmd_cast_i.data[0+:8]); - if (cprint_w_v_li[i] & mem_cmd_yumi_o) - $display("[CORE%0x PRT] %c", i, mem_cmd_cast_i.data[0+:8]); - if (finish_w_v_li[i] & mem_cmd_yumi_o & ~mem_cmd_cast_i.data[0]) - begin - $display("[CORE%0x FSH] PASS", i); - core_passed_debug <= 1; - end - if (finish_w_v_li[i] & mem_cmd_yumi_o & mem_cmd_cast_i.data[0]) - begin - $display("[CORE%0x FSH] FAIL", i); - core_failed_debug <=1; - end - end - - if (all_finished_r) - begin - $display("All cores finished! Terminating..."); - $finish(); - all_finished_debug_o <= 1; - end - if (reset_i) - begin - all_finished_debug_o <= 0; - core_passed_debug <= 0; - core_failed_debug <= 0; - end - end -bp_cce_mem_msg_s mem_resp_lo; -logic mem_resp_v_lo, mem_resp_ready_lo; -assign mem_cmd_yumi_o = mem_cmd_v_i & mem_resp_ready_lo; -bsg_one_fifo - #(.width_p(cce_mem_msg_width_lp)) - mem_resp_buffer - (.clk_i(clk_i) - ,.reset_i(reset_i) - - ,.data_i(mem_resp_lo) - ,.v_i(mem_cmd_yumi_o) - ,.ready_o(mem_resp_ready_lo) - - ,.data_o(mem_resp_o) - ,.v_o(mem_resp_v_lo) - ,.yumi_i(mem_resp_ready_i & mem_resp_v_lo) - ); -assign mem_resp_v_o = mem_resp_v_lo & mem_resp_ready_i; - -assign mem_resp_lo = - '{msg_type : mem_cmd_cast_i.msg_type - ,addr : mem_cmd_cast_i.addr - ,payload : mem_cmd_cast_i.payload - ,size : mem_cmd_cast_i.size - ,data : '0 - }; - - -endmodule : bp_nonsynth_host - diff --git a/litex/soc/cores/cpu/blackparrot/bp_software/cce_ucode.mem b/litex/soc/cores/cpu/blackparrot/bp_software/cce_ucode.mem deleted file mode 100644 index 5815a732..00000000 --- a/litex/soc/cores/cpu/blackparrot/bp_software/cce_ucode.mem +++ /dev/null @@ -1,96 +0,0 @@ -010001000001111100000000000000000000000001000000 -001000000001111100000000000010110000000000000000 -000001000000000011111000000000000000100000000000 -010001000011111100000000000000000000000000000010 -001000000011111100000000000000010000000000000000 -000001000010000111111000000000000000100000000000 -010001000101111100000000000000000000000000001000 -001000000101111100000000000001000000000000000000 -000001000100001011111000000000000000100000000000 -101001000000010010100110100000000000000000000000 -001111000000000000000000000001110000000000000000 -010001000001111100000000000000000000000000000000 -010001000011111100000000000000000000000000000010 -001101000010000000000000000110000000000000000000 -010001000101111100000000000000000000000000000000 -010001000111111100000000000000000000000001000000 -010001001001111100000000000000000000000000000000 -001101000110001000000000000101100000000000000000 -111001000001000001001100100100000000000000000000 -000000000100001011111000000000000000100000000000 -000000001000010011111000000000100000000000000000 -001111000000000000000000000100010000000000000000 -000000000000000011111000000000000000100000000000 -001111000000000000000000000011010000000000000000 -010001000001111100000000000000000000000000000000 -010001000011111100000000000000000000000000000010 -010001000111111100000000000000000000000000000000 -001101000010000000000000001000010000000000000000 -111001000000000010101100100100000000000000000000 -111010011001000000000000000000000000000000000000 -001001000110010000000000010111110000000000000000 -000000000000000011111000000000000000100000000000 -001111000000000000000000000110110000000000000000 -111000010000000000000000000000000000000000000000 -110001000000000000000000000000000000000000000000 -111011000000000000000000000000000000000000000000 -001010000011111100000000010110010000000000000001 -100000100000000000000000000000000000000000000000 -001010001001111100000000001000010000000000000001 -111010000000000000000000000000000000000000000000 -100001100010000000100000000000000000000000000000 -110000000000000000000000000000000000000000000000 -001010000001111100000000001100010000000000000001 -001010000101111100000000001011110000000000000001 -001010001101111100000000001011110000000000000001 -010100000001111100000000000000000000000000000010 -001111000000000000000000001100100000000000000000 -010100000001111100000000000000000000000000000001 -001111000000000000000000001100100000000000000000 -010100000001111100000000000000000000000000000110 -001010011011111100000000010000110000000000000000 -010001000001111100000000000000000000000000000000 -010001000011111100000000000000000000000000000010 -010001000101111100000000000000000000000000000000 -010001000111111100000000000000000000000000000001 -001101000010000000000000001111110000000000000000 -001011000001111100000000001111010000000000000000 -001011010000000000000000001111010000000000000000 -000000000100001011111000000000000000100000000000 -111001000110000010001010100100000000000000000000 -101010100000001010100100000000000000000000000000 -000000000000000011111000000000000000100000000000 -001111000000000000000000001101110000000000000000 -001000000101111100000000010000110000000000000000 -111010011001000000000000000000000000000000000000 -000001000100001011111000000000000000100000000000 -001111000000000000000000001111110000000000000000 -001010011001111100000000010001110000000000000000 -101010100010001000100000000000000000000000000000 -111001000101100010001000100100000000000000000000 -001111000000000000000000001000010000000000000000 -101001100010001001100010000000000000000000000000 -001010010111111100000000010011110000000000000000 -111001000011100010011011100100000000000000000000 -111011011000000000000000000000000000000000000000 -001010011101111100000000010011010000000000000001 -111001010100101010101100100000000000000000000000 -111010011000000000000000000000000000000000000000 -011000010110000000000000000000000000000000000000 -001010010101111100000000010101110000000000000000 -111001000010100110001001100100000000000000000000 -111001000011100110001001100100000000000000000000 -111011011000000000000000000000000000000000000000 -001010011101111100000000010101010000000000000001 -111001010100101010101100100100000000000000000000 -111010011000000000000000000000000000000000000000 -001111000000000000000000001000010000000000000000 -111001010000101010101100100100000000000000000000 -001111000000000000000000001000010000000000000000 -111010000000000000000000000000000000000000000000 -001010000001111100000000010111010000000000000001 -111001010000101010101100100100000000000000000000 -001111000000000000000000001000010000000000000000 -111001010000101010101100100100000000000000000000 -001111000000000000000000001000010000000000000000 -110111000000000000000000000000000000000000000000 diff --git a/litex/soc/cores/cpu/blackparrot/bp_software/udivmoddi4.c b/litex/soc/cores/cpu/blackparrot/bp_software/udivmoddi4.c deleted file mode 100644 index a57c6e0e..00000000 --- a/litex/soc/cores/cpu/blackparrot/bp_software/udivmoddi4.c +++ /dev/null @@ -1,358 +0,0 @@ -/* ===-- udivmoddi4.c - Implement __udivmoddi4 -----------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file implements __udivmoddi4 for the compiler_rt library. - * - * ===----------------------------------------------------------------------=== - */ - -#ifndef __blackparrot__ -#include "int_lib.h" - -/* Effects: if rem != 0, *rem = a % b - * Returns: a / b - */ - -/* Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide */ - -COMPILER_RT_ABI du_int -__udivmoddi4(du_int a, du_int b, du_int* rem) -{ - const unsigned n_uword_bits = sizeof(su_int) * CHAR_BIT; - const unsigned n_udword_bits = sizeof(du_int) * CHAR_BIT; - udwords n; - n.all = a; - udwords d; - d.all = b; - udwords q; - udwords r; - unsigned sr; - /* special cases, X is unknown, K != 0 */ - if (n.s.high == 0) - { - if (d.s.high == 0) - { - /* 0 X - * --- - * 0 X - */ - if (rem) - *rem = n.s.low % d.s.low; - return n.s.low / d.s.low; - } - /* 0 X - * --- - * K X - */ - if (rem) - *rem = n.s.low; - return 0; - } - /* n.s.high != 0 */ - if (d.s.low == 0) - { - if (d.s.high == 0) - { - /* K X - * --- - * 0 0 - */ - if (rem) - *rem = n.s.high % d.s.low; - return n.s.high / d.s.low; - } - /* d.s.high != 0 */ - if (n.s.low == 0) - { - /* K 0 - * --- - * K 0 - */ - if (rem) - { - r.s.high = n.s.high % d.s.high; - r.s.low = 0; - *rem = r.all; - } - return n.s.high / d.s.high; - } - /* K K - * --- - * K 0 - */ - if ((d.s.high & (d.s.high - 1)) == 0) /* if d is a power of 2 */ - { - if (rem) - { - r.s.low = n.s.low; - r.s.high = n.s.high & (d.s.high - 1); - *rem = r.all; - } - return n.s.high >> __builtin_ctz(d.s.high); - } - /* K K - * --- - * K 0 - */ - sr = __builtin_clz(d.s.high) - __builtin_clz(n.s.high); - /* 0 <= sr <= n_uword_bits - 2 or sr large */ - if (sr > n_uword_bits - 2) - { - if (rem) - *rem = n.all; - return 0; - } - ++sr; - /* 1 <= sr <= n_uword_bits - 1 */ - /* q.all = n.all << (n_udword_bits - sr); */ - q.s.low = 0; - q.s.high = n.s.low << (n_uword_bits - sr); - /* r.all = n.all >> sr; */ - r.s.high = n.s.high >> sr; - r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); - } - else /* d.s.low != 0 */ - { - if (d.s.high == 0) - { - /* K X - * --- - * 0 K - */ - if ((d.s.low & (d.s.low - 1)) == 0) /* if d is a power of 2 */ - { - if (rem) - *rem = n.s.low & (d.s.low - 1); - if (d.s.low == 1) - return n.all; - sr = __builtin_ctz(d.s.low); - q.s.high = n.s.high >> sr; - q.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); - return q.all; - } - /* K X - * --- - * 0 K - */ - sr = 1 + n_uword_bits + __builtin_clz(d.s.low) - __builtin_clz(n.s.high); - /* 2 <= sr <= n_udword_bits - 1 - * q.all = n.all << (n_udword_bits - sr); - * r.all = n.all >> sr; - */ - if (sr == n_uword_bits) - { - q.s.low = 0; - q.s.high = n.s.low; - r.s.high = 0; - r.s.low = n.s.high; - } - else if (sr < n_uword_bits) // 2 <= sr <= n_uword_bits - 1 - { - q.s.low = 0; - q.s.high = n.s.low << (n_uword_bits - sr); - r.s.high = n.s.high >> sr; - r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); - } - else // n_uword_bits + 1 <= sr <= n_udword_bits - 1 - { - q.s.low = n.s.low << (n_udword_bits - sr); - q.s.high = (n.s.high << (n_udword_bits - sr)) | - (n.s.low >> (sr - n_uword_bits)); - r.s.high = 0; - r.s.low = n.s.high >> (sr - n_uword_bits); - } - } - else - { - /* K X - * --- - * K K - */ - sr = __builtin_clz(d.s.high) - __builtin_clz(n.s.high); - /* 0 <= sr <= n_uword_bits - 1 or sr large */ - if (sr > n_uword_bits - 1) - { - if (rem) - *rem = n.all; - return 0; - } - ++sr; - /* 1 <= sr <= n_uword_bits */ - /* q.all = n.all << (n_udword_bits - sr); */ - q.s.low = 0; - if (sr == n_uword_bits) - { - q.s.high = n.s.low; - r.s.high = 0; - r.s.low = n.s.high; - } - else - { - q.s.high = n.s.low << (n_uword_bits - sr); - r.s.high = n.s.high >> sr; - r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); - } - } - } - /* Not a special case - * q and r are initialized with: - * q.all = n.all << (n_udword_bits - sr); - * r.all = n.all >> sr; - * 1 <= sr <= n_udword_bits - 1 - */ - su_int carry = 0; - for (; sr > 0; --sr) - { - /* r:q = ((r:q) << 1) | carry */ - r.s.high = (r.s.high << 1) | (r.s.low >> (n_uword_bits - 1)); - r.s.low = (r.s.low << 1) | (q.s.high >> (n_uword_bits - 1)); - q.s.high = (q.s.high << 1) | (q.s.low >> (n_uword_bits - 1)); - q.s.low = (q.s.low << 1) | carry; - /* carry = 0; - * if (r.all >= d.all) - * { - * r.all -= d.all; - * carry = 1; - * } - */ - const di_int s = (di_int)(d.all - r.all - 1) >> (n_udword_bits - 1); - carry = s & 1; - r.all -= d.all & s; - } - q.all = (q.all << 1) | carry; - if (rem) - *rem = r.all; - return q.all; -} -#else - -/* More subroutines needed by GCC output code on some machines. */ -/* Compile this one with gcc. */ -/* Copyright (C) 1989-2014 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 3, or (at your option) any later -version. - -GCC is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -/* This is extracted from gcc's libgcc/libgcc2.c with these typedefs added: */ -typedef short Wtype; -typedef int DWtype; -typedef unsigned int UWtype; -typedef unsigned long long UDWtype; -#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__ -struct DWstruct {Wtype high, low;}; -#else -struct DWstruct {Wtype low, high;}; -#endif -typedef union { - struct DWstruct s; - DWtype ll; -} DWunion; - -UDWtype -__udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp) -{ - UDWtype q = 0, r = n, y = d; - UWtype lz1, lz2, i, k; - - /* Implements align divisor shift dividend method. This algorithm - aligns the divisor under the dividend and then perform number of - test-subtract iterations which shift the dividend left. Number of - iterations is k + 1 where k is the number of bit positions the - divisor must be shifted left to align it under the dividend. - quotient bits can be saved in the rightmost positions of the dividend - as it shifts left on each test-subtract iteration. */ - - if (y <= r) - { - lz1 = __builtin_clzll (d); - lz2 = __builtin_clzll (n); - - k = lz1 - lz2; - y = (y << k); - - /* Dividend can exceed 2 ^ (width − 1) − 1 but still be less than the - aligned divisor. Normal iteration can drops the high order bit - of the dividend. Therefore, first test-subtract iteration is a - special case, saving its quotient bit in a separate location and - not shifting the dividend. */ - if (r >= y) - { - r = r - y; - q = (1ULL << k); - } - - if (k > 0) - { - y = y >> 1; - - /* k additional iterations where k regular test subtract shift - dividend iterations are done. */ - i = k; - do - { - if (r >= y) - r = ((r - y) << 1) + 1; - else - r = (r << 1); - i = i - 1; - } while (i != 0); - - /* First quotient bit is combined with the quotient bits resulting - from the k regular iterations. */ - q = q + r; - r = r >> k; - q = q - (r << k); - } - } - - if (rp) - *rp = r; - return q; -} - -DWtype -__moddi3 (DWtype u, DWtype v) -{ - Wtype c = 0; - DWunion uu = {.ll = u}; - DWunion vv = {.ll = v}; - DWtype w; - - if (uu.s.high < 0) - c = ~c, - uu.ll = -uu.ll; - if (vv.s.high < 0) - vv.ll = -vv.ll; - - (void) __udivmoddi4 (uu.ll, vv.ll, (UDWtype*)&w); - if (c) - w = -w; - - return w; -} - -#endif diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 5a9738d0..6b15a964 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -40,7 +40,7 @@ from litex.soc.cores.cpu import CPU CPU_VARIANTS = { "standard": "freechips.rocketchip.system.LitexConfig", } -# -mcmodel=medany + GCC_FLAGS = { "standard": "-march=rv64ia -mabi=lp64 -O0 ", } @@ -104,7 +104,6 @@ class BlackParrotRV64(CPU): o_wbm_we_o = idbus.we, o_wbm_cti_o = idbus.cti, o_wbm_bte_o = idbus.bte, - ) # add verilog sources @@ -120,7 +119,7 @@ class BlackParrotRV64(CPU): def add_sources(platform, variant="standard"): vdir = get_data_mod("cpu", "blackparrot").data_location bp_litex_dir = os.path.join(vdir,"bp_litex") - simulation = 0 + simulation = 1 if (simulation == 1): filename= os.path.join(bp_litex_dir,"flist.verilator") else: @@ -137,7 +136,6 @@ class BlackParrotRV64(CPU): a = os.popen('echo '+ str(dir_)) dir_start = a.read() vdir = dir_start[:-1] + line[s2:-1] - #print("INCDIR" + vdir) platform.add_verilog_include_path(vdir) #this line might be changed elif (temp[0]=='$') : s2 = line.find('/') @@ -145,7 +143,6 @@ class BlackParrotRV64(CPU): a = os.popen('echo '+ str(dir_)) dir_start = a.read() vdir = dir_start[:-1]+ line[s2:-1] - #print(vdir) platform.add_source(vdir) #this line might be changed elif (temp[0] == '/'): assert("No support for absolute path for now") diff --git a/litex/soc/cores/cpu/blackparrot/flist.fpga b/litex/soc/cores/cpu/blackparrot/flist.fpga deleted file mode 100644 index 6ca19de8..00000000 --- a/litex/soc/cores/cpu/blackparrot/flist.fpga +++ /dev/null @@ -1,250 +0,0 @@ -+incdir+$BASEJUMP_STL_DIR/bsg_dataflow -+incdir+$BASEJUMP_STL_DIR/bsg_mem -+incdir+$BASEJUMP_STL_DIR/bsg_misc -+incdir+$BASEJUMP_STL_DIR/bsg_test -+incdir+$BASEJUMP_STL_DIR/bsg_noc -+incdir+$BP_COMMON_DIR/src/include -+incdir+$BP_FE_DIR/src/include -+incdir+$BP_BE_DIR/src/include -+incdir+$BP_BE_DIR/src/include/bp_be_dcache -+incdir+$BP_ME_DIR/src/include/v -+incdir+$BP_TOP_DIR/src/include -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_pkg.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v -$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh -$BP_COMMON_DIR/src/include/bp_common_pkg.vh -$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh -$BP_COMMON_DIR/src/include/bp_common_cfg_link_pkg.vh -$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh -$BP_FE_DIR/src/include/bp_fe_pkg.vh -$BP_BE_DIR/src/include/bp_be_pkg.vh -$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh -$BP_ME_DIR/src/include/v/bp_cce_pkg.v -$BP_ME_DIR/src/include/v/bp_me_pkg.vh -$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v -$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v -$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_dma.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_miss.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_decode.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf_queue.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_1_to_n.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_full.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v -//$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v -$BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_buf.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_en.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en_bypass.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank_reverse.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_muxi2_gatestack.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_nor3.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_nand.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce_segmented.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_strobe.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_xnor.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v -$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v -$BP_COMMON_DIR/src/v/bp_pma.v -$BP_COMMON_DIR/src/v/bp_tlb.v -$BP_COMMON_DIR/src/v/bp_tlb_replacement.v -$BP_BE_DIR/src/v/bp_be_top.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v -$BP_FE_DIR/src/v/bp_fe_bht.v -$BP_FE_DIR/src/v/bp_fe_btb.v -$BP_FE_DIR/src/v/bp_fe_lce_cmd.v -$BP_FE_DIR/src/v/bp_fe_icache.v -$BP_FE_DIR/src/v/bp_fe_instr_scan.v -$BP_FE_DIR/src/v/bp_fe_lce.v -$BP_FE_DIR/src/v/bp_fe_lce_req.v -$BP_FE_DIR/src/v/bp_fe_mem.v -$BP_FE_DIR/src/v/bp_fe_pc_gen.v -$BP_FE_DIR/src/v/bp_fe_top.v -$BP_ME_DIR/src/v/cache/bp_me_cache_dma_to_cce.v -$BP_ME_DIR/src/v/cache/bp_me_cache_slice.v -$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache.v -$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache_buffered.v -$BP_ME_DIR/src/v/cce/bp_cce.v -$BP_ME_DIR/src/v/cce/bp_cce_alu.v -$BP_ME_DIR/src/v/cce/bp_cce_buffered.v -$BP_ME_DIR/src/v/cce/bp_cce_dir.v -$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v -$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v -$BP_ME_DIR/src/v/cce/bp_cce_gad.v -$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v -$BP_ME_DIR/src/v/cce/bp_cce_msg.v -$BP_ME_DIR/src/v/cce/bp_cce_msg_cached.v -$BP_ME_DIR/src/v/cce/bp_cce_msg_uncached.v -$BP_ME_DIR/src/v/cce/bp_cce_pc.v -$BP_ME_DIR/src/v/cce/bp_cce_pending.v -$BP_ME_DIR/src/v/cce/bp_cce_reg.v -$BP_ME_DIR/src/v/cce/bp_cce_spec.v -$BP_ME_DIR/src/v/cce/bp_io_cce.v -$BP_ME_DIR/src/v/cce/bp_uce.v -$BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_client.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_master.v -$BP_ME_DIR/src/v/wormhole/bp_me_cord_to_id.v -$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v -//$BP_TOP_DIR/src/v/bp_accelerator_complex.v -$BP_TOP_DIR/src/v/bp_cfg.v -$BP_TOP_DIR/src/v/bp_cfg_buffered.v -$BP_TOP_DIR/src/v/bp_core.v -//$BP_TOP_DIR/src/v/bp_core_complex.v -$BP_TOP_DIR/src/v/bp_core_minimal.v -//$BP_TOP_DIR/src/v/bp_clint.v -$BP_TOP_DIR/src/v/bp_clint_node.v -$BP_TOP_DIR/src/v/bp_clint_slice.v -$BP_TOP_DIR/src/v/bp_clint_slice_buffered.v -//$BP_TOP_DIR/src/v/bp_l2e_tile.v -//$BP_TOP_DIR/src/v/bp_l2e_tile_node.v -$BP_TOP_DIR/src/v/bp_io_complex.v -$BP_TOP_DIR/src/v/bp_io_link_to_lce.v -$BP_TOP_DIR/src/v/bp_io_tile.v -$BP_TOP_DIR/src/v/bp_io_tile_node.v -$BP_TOP_DIR/src/v/bp_mem_complex.v -//$BP_TOP_DIR/src/v/bp_processor.v -$BP_TOP_DIR/src/v/bp_softcore.v -//$BP_TOP_DIR/src/v/bp_tile.v -//$BP_TOP_DIR/src/v/bp_tile_node.v -$BP_TOP_DIR/src/v/bsg_async_noc_link.v -//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_reset_gen.v -//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_clock_gen.v -//$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_calc_tracer.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_dcache_tracer.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_perf.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_npc_tracer.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_vm_tracer.v -//$BP_ME_DIR/test/common/bp_mem.v -//$BP_ME_DIR/test/common/bp_mem_transducer.v -//$BP_ME_DIR/test/common/bp_mem_delay_model.v -//$BP_ME_DIR/test/common/bp_mem_storage_sync.v -//$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v -//$BP_ME_DIR/test/common/dramsim2_wrapper.cpp -//$BP_ME_DIR/test/common/bp_mem_utils.cpp -//$BP_ME_DIR/test/common/bp_cce_nonsynth_tracer.v -$BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v -//$BP_TOP_DIR/test/common/bp_nonsynth_cosim.v -//$BP_TOP_DIR/test/common/bp_nonsynth_host.v -//$BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v -$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v -//$BP_TOP_DIR/test/common/bp_nonsynth_nbf_loader.v -//$BP_TOP_DIR/test/common/bp_monitor.cpp -//$BP_TOP_DIR/test/common/dromajo_cosim.cpp -//$BP_FPGA_DIR/wrapper.v -$BP_FPGA_DIR/bp2wb_convertor.v -$BP_FPGA_DIR/fpga/ExampleBlackParrotSystem.v diff --git a/litex/soc/cores/cpu/blackparrot/flist.verilator b/litex/soc/cores/cpu/blackparrot/flist.verilator deleted file mode 100644 index 551f5ea5..00000000 --- a/litex/soc/cores/cpu/blackparrot/flist.verilator +++ /dev/null @@ -1,250 +0,0 @@ -+incdir+$BASEJUMP_STL_DIR/bsg_dataflow -+incdir+$BASEJUMP_STL_DIR/bsg_mem -+incdir+$BASEJUMP_STL_DIR/bsg_misc -+incdir+$BASEJUMP_STL_DIR/bsg_test -+incdir+$BASEJUMP_STL_DIR/bsg_noc -+incdir+$BP_COMMON_DIR/src/include -+incdir+$BP_FE_DIR/src/include -+incdir+$BP_BE_DIR/src/include -+incdir+$BP_BE_DIR/src/include/bp_be_dcache -+incdir+$BP_ME_DIR/src/include/v -+incdir+$BP_TOP_DIR/src/include -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_pkg.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v -$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh -$BP_COMMON_DIR/src/include/bp_common_pkg.vh -$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh -$BP_COMMON_DIR/src/include/bp_common_cfg_link_pkg.vh -$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh -$BP_FE_DIR/src/include/bp_fe_pkg.vh -$BP_BE_DIR/src/include/bp_be_pkg.vh -$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh -$BP_ME_DIR/src/include/v/bp_cce_pkg.v -$BP_ME_DIR/src/include/v/bp_me_pkg.vh -$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v -$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v -$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_dma.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_miss.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_decode.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf.v -$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf_queue.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_1_to_n.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_full.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v -//$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v -$BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_buf.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_en.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en_bypass.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank_reverse.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_muxi2_gatestack.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_nor3.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_nand.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce_segmented.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_strobe.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_xnor.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v -$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v -$BP_COMMON_DIR/src/v/bp_pma.v -$BP_COMMON_DIR/src/v/bp_tlb.v -$BP_COMMON_DIR/src/v/bp_tlb_replacement.v -$BP_BE_DIR/src/v/bp_be_top.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v -$BP_FE_DIR/src/v/bp_fe_bht.v -$BP_FE_DIR/src/v/bp_fe_btb.v -$BP_FE_DIR/src/v/bp_fe_lce_cmd.v -$BP_FE_DIR/src/v/bp_fe_icache.v -$BP_FE_DIR/src/v/bp_fe_instr_scan.v -$BP_FE_DIR/src/v/bp_fe_lce.v -$BP_FE_DIR/src/v/bp_fe_lce_req.v -$BP_FE_DIR/src/v/bp_fe_mem.v -$BP_FE_DIR/src/v/bp_fe_pc_gen.v -$BP_FE_DIR/src/v/bp_fe_top.v -$BP_ME_DIR/src/v/cache/bp_me_cache_dma_to_cce.v -$BP_ME_DIR/src/v/cache/bp_me_cache_slice.v -$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache.v -$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache_buffered.v -$BP_ME_DIR/src/v/cce/bp_cce.v -$BP_ME_DIR/src/v/cce/bp_cce_alu.v -$BP_ME_DIR/src/v/cce/bp_cce_buffered.v -$BP_ME_DIR/src/v/cce/bp_cce_dir.v -$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v -$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v -$BP_ME_DIR/src/v/cce/bp_cce_gad.v -$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v -$BP_ME_DIR/src/v/cce/bp_cce_msg.v -$BP_ME_DIR/src/v/cce/bp_cce_msg_cached.v -$BP_ME_DIR/src/v/cce/bp_cce_msg_uncached.v -$BP_ME_DIR/src/v/cce/bp_cce_pc.v -$BP_ME_DIR/src/v/cce/bp_cce_pending.v -$BP_ME_DIR/src/v/cce/bp_cce_reg.v -$BP_ME_DIR/src/v/cce/bp_cce_spec.v -$BP_ME_DIR/src/v/cce/bp_io_cce.v -$BP_ME_DIR/src/v/cce/bp_uce.v -$BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_client.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_master.v -$BP_ME_DIR/src/v/wormhole/bp_me_cord_to_id.v -$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v -//$BP_TOP_DIR/src/v/bp_accelerator_complex.v -$BP_TOP_DIR/src/v/bp_cfg.v -$BP_TOP_DIR/src/v/bp_cfg_buffered.v -$BP_TOP_DIR/src/v/bp_core.v -//$BP_TOP_DIR/src/v/bp_core_complex.v -$BP_TOP_DIR/src/v/bp_core_minimal.v -//$BP_TOP_DIR/src/v/bp_clint.v -$BP_TOP_DIR/src/v/bp_clint_node.v -$BP_TOP_DIR/src/v/bp_clint_slice.v -$BP_TOP_DIR/src/v/bp_clint_slice_buffered.v -//$BP_TOP_DIR/src/v/bp_l2e_tile.v -//$BP_TOP_DIR/src/v/bp_l2e_tile_node.v -$BP_TOP_DIR/src/v/bp_io_complex.v -$BP_TOP_DIR/src/v/bp_io_link_to_lce.v -$BP_TOP_DIR/src/v/bp_io_tile.v -$BP_TOP_DIR/src/v/bp_io_tile_node.v -$BP_TOP_DIR/src/v/bp_mem_complex.v -//$BP_TOP_DIR/src/v/bp_processor.v -$BP_TOP_DIR/src/v/bp_softcore.v -//$BP_TOP_DIR/src/v/bp_tile.v -//$BP_TOP_DIR/src/v/bp_tile_node.v -$BP_TOP_DIR/src/v/bsg_async_noc_link.v -//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_reset_gen.v -//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_clock_gen.v -//$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_calc_tracer.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_dcache_tracer.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_perf.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_npc_tracer.v -//$BP_BE_DIR/test/common/bp_be_nonsynth_vm_tracer.v -//$BP_ME_DIR/test/common/bp_mem.v -//$BP_ME_DIR/test/common/bp_mem_transducer.v -//$BP_ME_DIR/test/common/bp_mem_delay_model.v -//$BP_ME_DIR/test/common/bp_mem_storage_sync.v -//$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v -//$BP_ME_DIR/test/common/dramsim2_wrapper.cpp -//$BP_ME_DIR/test/common/bp_mem_utils.cpp -//$BP_ME_DIR/test/common/bp_cce_nonsynth_tracer.v -$BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v -//$BP_TOP_DIR/test/common/bp_nonsynth_cosim.v -//$BP_TOP_DIR/test/common/bp_nonsynth_host.v -//$BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v -$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v -//$BP_TOP_DIR/test/common/bp_nonsynth_nbf_loader.v -//$BP_TOP_DIR/test/common/bp_monitor.cpp -//$BP_TOP_DIR/test/common/dromajo_cosim.cpp -//$BP_FPGA_DIR/wrapper.v -$BP_FPGA_DIR/bp2wb_convertor.v -$BP_FPGA_DIR/simulation/ExampleBlackParrotSystem.v diff --git a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator b/litex/soc/cores/cpu/blackparrot/flist_litex.verilator deleted file mode 100644 index ba656dc1..00000000 --- a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator +++ /dev/null @@ -1,229 +0,0 @@ -//// Includes -// bsg_ip_cores includes -+incdir+$BASEJUMP_STL_DIR/bsg_dataflow -+incdir+$BASEJUMP_STL_DIR/bsg_mem -+incdir+$BASEJUMP_STL_DIR/bsg_misc -+incdir+$BASEJUMP_STL_DIR/bsg_test -+incdir+$BASEJUMP_STL_DIR/bsg_noc -// common includes -+incdir+$BP_COMMON_DIR/src/include -// fe includes -+incdir+$BP_FE_DIR/src/include -// be includes -+incdir+$BP_BE_DIR/src/include -+incdir+$BP_BE_DIR/src/include/bp_be_dcache -// me includes -+incdir+$BP_ME_DIR/src/include/v -// top includes -+incdir+$BP_TOP_DIR/src/include -//// Packages -// bsg_ip_cores packages -$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v -// Interface packages -$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh -$BP_COMMON_DIR/src/include/bp_common_pkg.vh -$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh -// FE packages -$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh -$BP_FE_DIR/src/include/bp_fe_pkg.vh -// BE packages -$BP_BE_DIR/src/include/bp_be_pkg.vh -$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh -// ME packages -$BP_ME_DIR/src/include/v/bp_cce_pkg.v -$BP_ME_DIR/src/include/v/bp_me_pkg.vh -// Top packages -$BP_TOP_DIR/src/include/bp_cfg_link_pkg.vh -//// bsg_ip_cores files -$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v -$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v -$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v -$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v -// $BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v -$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v -$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_router.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_router_buffered.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v -$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v -// Common files -$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_fence.v -$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v -$BP_COMMON_DIR/src/v/bp_tlb.v -$BP_COMMON_DIR/src/v/bp_tlb_replacement.v -// BE files -$BP_BE_DIR/src/v/bp_be_top.v -// Calculator -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v -$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v -// Checker -$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v -$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v -// MMU -$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v -$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v -//// FE files -$BP_FE_DIR/src/v/bp_fe_bht.v -$BP_FE_DIR/src/v/bp_fe_btb.v -$BP_FE_DIR/src/v/bp_fe_lce_cmd.v -$BP_FE_DIR/src/v/bp_fe_icache.v -$BP_FE_DIR/src/v/bp_fe_instr_scan.v -$BP_FE_DIR/src/v/bp_fe_lce.v -$BP_FE_DIR/src/v/bp_fe_lce_req.v -$BP_FE_DIR/src/v/bp_fe_mem.v -$BP_FE_DIR/src/v/bp_fe_pc_gen.v -$BP_FE_DIR/src/v/bp_fe_top.v -//// ME files -// CCE -$BP_ME_DIR/src/v/cce/bp_cce.v -$BP_ME_DIR/src/v/cce/bp_cce_alu.v -$BP_ME_DIR/src/v/cce/bp_cce_dir.v -$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v -$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v -$BP_ME_DIR/src/v/cce/bp_cce_gad.v -$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v -$BP_ME_DIR/src/v/cce/bp_cce_msg.v -$BP_ME_DIR/src/v/cce/bp_cce_msg_cached.v -$BP_ME_DIR/src/v/cce/bp_cce_msg_uncached.v -$BP_ME_DIR/src/v/cce/bp_cce_pc.v -$BP_ME_DIR/src/v/cce/bp_cce_pending.v -$BP_ME_DIR/src/v/cce/bp_cce_reg.v -$BP_ME_DIR/src/v/cce/bp_cce_top.v -// Network -$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_wormhole_link_client.v -$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_wormhole_link_master.v -$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v -$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v -//// TOP -$BP_TOP_DIR/src/v/bp_chip.v -$BP_TOP_DIR/src/v/bp_core.v -$BP_TOP_DIR/src/v/bp_core_complex.v -$BP_TOP_DIR/src/v/bp_mem_complex.v -$BP_TOP_DIR/src/v/bp_mmio_enclave.v -$BP_TOP_DIR/src/v/bp_mmio_node.v -$BP_TOP_DIR/src/v/bp_tile.v -$BP_TOP_DIR/src/v/bp_tile_node.v -//// Common -$BP_COMMON_DIR/src/v/bp_addr_map.v - -// bsg_ip_cores files -$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v -// be files -//$BP_BE_DIR/test/common/bp_be_nonsynth_tracer.v -// $BP_BE_DIR/test/common/bp_be_nonsynth_perf.v -// me files -// $BP_ME_DIR/test/common/bp_mem.v -// $BP_ME_DIR/test/common/bp_mem_delay_model.v -// $BP_ME_DIR/test/common/bp_mem_transducer.v -// $BP_ME_DIR/test/common/bp_mem_storage_sync.v -// $BP_ME_DIR/test/common/dramsim2_wrapper.cpp -$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v -// $BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v -// $BP_ME_DIR/test/common/bp_cce_nonsynth_tracer.v -// $BP_ME_DIR/test/common/bp_mem_utils.cpp -// top files -$BP_TOP_DIR/test/common/bp_nonsynth_host.v -// $BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v -//$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v -// /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/wrapper.v -// /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/test_bp.cpp -$BP_TOP_DIR/test/common/bp_monitor.cpp -$BP_FPGA_DIR/bp2wb_convertor.v -$BP_FPGA_DIR/ExampleBlackParrotSystem.v -$BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v -// Recent -$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v diff --git a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh index 1e45ca90..0f6fa126 100755 --- a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh +++ b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh @@ -15,10 +15,10 @@ export BP_EXTERNAL_DIR=$BP/external export BASEJUMP_STL_DIR=$BP_EXTERNAL_DIR/basejump_stl export LITEX_FPGA_DIR=$BP_LITEX_DIR/fpga export LITEX_SIMU_DIR=$BP_LITEX_DIR/simulation -export LITEX_SOFTWARE=$BP_LITEX_DIR/software +export BP_LITEX_SOFTWARE=$BP_LITEX_DIR/software ##SOFTWARE CHANGES## #for a reason, provided udivmoddi4.c is not functionally correct when used with either BP or Rocket under IA extension. Another version of udivmoddi4.c is a workaround to run BIOS on these architectures. -cp $LITEX_SOFTWARE/udivmoddi4.c $LITEX_SOFTWARE_COMPILER_RT/pythondata_software_compiler_rt/data/lib/builtins/. +cp $BP_LITEX_SOFTWARE/udivmoddi4.c $LITEX_SOFTWARE_COMPILER_RT/pythondata_software_compiler_rt/data/lib/builtins/. diff --git a/litex/soc/cores/cpu/blackparrot/update_BP.sh b/litex/soc/cores/cpu/blackparrot/update_BP.sh deleted file mode 100755 index c6ddde97..00000000 --- a/litex/soc/cores/cpu/blackparrot/update_BP.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - - -##SOFTWARE CHANGES## - -#for a reason, provided udivmoddi4.c is not functionally correct when used with either BP or Rocket under IA extension. Another version of udivmoddi4.c is a workaround to run BIOS on these architectures. -cp bp_software/udivmoddi4.c $LITEX/litex/soc/software/compiler_rt/lib/builtins/. -cp bp_software/cce_ucode.mem /tmp/. - -##HARDWARE CHANGES## -#Need to change some files because of memory map differences and proper syntesis -cp bp_hardware/bp_common_pkg.vh $BP_COMMON_DIR/src/include/. -cp bp_hardware/bp_cce_mmio_cfg_loader.v $BP_ME_DIR/test/common/. -cp bp_hardware/bp_nonsynth_host.v $BP_TOP_DIR/test/common/. - -# Neccessary files for FPGA Implementations -cp -r bp_fpga $BP_TOP/DIR diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile index cc58ddf3..4d6bc6f7 100755 --- a/litex/soc/software/bios/Makefile +++ b/litex/soc/software/bios/Makefile @@ -2,7 +2,7 @@ include ../include/generated/variables.mak include $(SOC_DIRECTORY)/software/common.mak ifeq ($(CPU),blackparrot) -BP_LIBS = -L$(LITEX_SOFTWARE) +BP_LIBS = -L$(BP_LITEX_SOFTWARE) BP_FLAGS = -lgcc endif # Permit TFTP_SERVER_PORT override from shell environment / command line diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c index 274cd789..08b3be4a 100644 --- a/litex/soc/software/bios/boot.c +++ b/litex/soc/software/bios/boot.c @@ -32,8 +32,6 @@ #include "sfl.h" #include "boot.h" -#define MEMTEST_DATA_SIZE2 (589824*4) - extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) @@ -61,16 +59,7 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u mtspr(SPR_EVBAR, addr); addr += 0x100; #endif - - -/* volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE; - int i; - unsigned int rdata; - for(i=0;i='0') && (c<='9')) return 1; - return 0; -} +#define isdigit(c) ((__ismask(c)&(_D)) != 0) #define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) #define islower(c) ((__ismask(c)&(_L)) != 0) #define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) diff --git a/litex/soc/software/libbase/libc.c b/litex/soc/software/libbase/libc.c index 698ec59c..be48cf65 100644 --- a/litex/soc/software/libbase/libc.c +++ b/litex/soc/software/libbase/libc.c @@ -23,7 +23,7 @@ #include #include #include -#include + /** * strchr - Find the first occurrence of a character in a string * @s: The string to be searched @@ -375,7 +375,7 @@ void *memchr(const void *s, int c, size_t n) * @base: The number base to use */ unsigned long strtoul(const char *nptr, char **endptr, int base) -{ printf("HI\n"); +{ unsigned long result = 0,value; if (!base) { @@ -392,14 +392,11 @@ unsigned long strtoul(const char *nptr, char **endptr, int base) if (nptr[0] == '0' && toupper(nptr[1]) == 'X') nptr += 2; } - printf("HI2\n"); while (isxdigit(*nptr) && (value = isdigit(*nptr) ? *nptr-'0' : toupper(*nptr)-'A'+10) < base) { result = result*base + value; nptr++; - printf("HI4\n"); } - printf("HI3\n"); if (endptr) *endptr = (char *)nptr; return result; diff --git a/litex/soc/software/libnet/tftp.c b/litex/soc/software/libnet/tftp.c index d5110738..439b3e07 100644 --- a/litex/soc/software/libnet/tftp.c +++ b/litex/soc/software/libnet/tftp.c @@ -117,11 +117,10 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, int i; int length_before; int spin = 0; - printf("DEBUGWTH?\n"); if(!microudp_arp_resolve(ip)) return -1; - printf("DEBUG0\n"); + microudp_set_callback(rx_callback); dst_buffer = buffer; @@ -130,8 +129,6 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, transfer_finished = 0; tries = 5; while(1) { - - printf("DEBUG1\n"); packet_data = microudp_get_tx_buffer(); len = format_request(packet_data, TFTP_RRQ, filename); microudp_send(PORT_IN, server_port, len); @@ -139,8 +136,6 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, microudp_service(); if((total_length > 0) || transfer_finished) break; } - - printf("DEBUG2\n"); if((total_length > 0) || transfer_finished) break; tries--; if(tries == 0) { @@ -149,7 +144,6 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, } } - printf("DEBUG3\n"); i = 12000000; length_before = total_length; while(!transfer_finished) { @@ -168,10 +162,8 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, microudp_service(); } - printf("DEBUG4\n"); microudp_set_callback(NULL); - printf("DEBUG5\n"); return total_length; } diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 86c6d969..987681d3 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -177,7 +177,6 @@ class SimSoC(SoCSDRAM): ident = "LiteX Simulation", ident_version=True, l2_reverse = False, **kwargs) -# self.add_constant("UART_POLLING",None) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) @@ -353,8 +352,8 @@ def main(): with_analyzer = args.with_analyzer, sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness), **soc_kwargs) - if args.ram_init is not None: #sdram_init - soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000) + if args.ram_init is not None: + soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) if args.with_ethernet: for i in range(4): soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))