From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 12:28:40 +0000 (+0100)
Subject: tidyup, use FPModBaseChain and FPModBase
X-Git-Tag: ls180-24jan2020~628
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c7ad21c2a540928898a25543a0a2b4bce57f177;p=ieee754fpu.git

tidyup, use FPModBaseChain and FPModBase
---

diff --git a/src/ieee754/fcvt/downsize.py b/src/ieee754/fcvt/downsize.py
index d7861880..4a23adee 100644
--- a/src/ieee754/fcvt/downsize.py
+++ b/src/ieee754/fcvt/downsize.py
@@ -1,9 +1,10 @@
 # IEEE754 Floating Point Conversion
 # Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
-from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
+from nmigen import Module, Signal, Const
 from nmigen.cli import main, verilog
 
+from ieee754.fpcommon.modbase import FPModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpcommon.msbhigh import FPMSBHigh
@@ -12,14 +13,13 @@ from ieee754.fpcommon.exphigh import FPEXPHigh
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTDownConvertMod(Elaboratable):
+class FPCVTDownConvertMod(FPModBase):
     """ FP down-conversion (higher to lower bitwidth)
     """
     def __init__(self, in_pspec, out_pspec):
         self.in_pspec = in_pspec
         self.out_pspec = out_pspec
-        self.i = self.ispec()
-        self.o = self.ospec()
+        super().__init__(in_pspec, "downconvert")
 
     def ispec(self):
         return FPADDBaseData(self.in_pspec)
@@ -27,15 +27,6 @@ class FPCVTDownConvertMod(Elaboratable):
     def ospec(self):
         return FPAddStage1Data(self.out_pspec, e_extra=True)
 
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.downconvert = self
-        m.d.comb += self.i.eq(i)
-
-    def process(self, i):
-        return self.o
-
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
@@ -124,5 +115,3 @@ class FPCVTDownConvertMod(Elaboratable):
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m
-
-
diff --git a/src/ieee754/fcvt/int2float.py b/src/ieee754/fcvt/int2float.py
index 8d45513b..889c301c 100644
--- a/src/ieee754/fcvt/int2float.py
+++ b/src/ieee754/fcvt/int2float.py
@@ -1,9 +1,10 @@
 # IEEE Floating Point Conversion
 # Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
-from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
+from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
+from ieee754.fpcommon.modbase import FPModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpcommon.msbhigh import FPMSBHigh
@@ -11,7 +12,7 @@ from ieee754.fpcommon.msbhigh import FPMSBHigh
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTIntToFloatMod(Elaboratable):
+class FPCVTIntToFloatMod(FPModBase):
     """ FP integer conversion: copes with 16/32/64 int to 16/32/64 fp.
 
         self.ctx.i.op & 0x1 == 0x1 : SIGNED int
@@ -20,8 +21,7 @@ class FPCVTIntToFloatMod(Elaboratable):
     def __init__(self, in_pspec, out_pspec):
         self.in_pspec = in_pspec
         self.out_pspec = out_pspec
-        self.i = self.ispec()
-        self.o = self.ospec()
+        super().__init__(in_pspec, "intconvert")
 
     def ispec(self):
         return FPADDBaseData(self.in_pspec)
@@ -29,15 +29,6 @@ class FPCVTIntToFloatMod(Elaboratable):
     def ospec(self):
         return FPAddStage1Data(self.out_pspec, e_extra=True)
 
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.intconvert = self
-        m.d.comb += self.i.eq(i)
-
-    def process(self, i):
-        return self.o
-
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
diff --git a/src/ieee754/fcvt/upsize.py b/src/ieee754/fcvt/upsize.py
index d8b9127e..e08aaf32 100644
--- a/src/ieee754/fcvt/upsize.py
+++ b/src/ieee754/fcvt/upsize.py
@@ -5,22 +5,22 @@
 import sys
 import functools
 
-from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
+from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
+from ieee754.fpcommon.modbase import FPModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTUpConvertMod(Elaboratable):
+class FPCVTUpConvertMod(FPModBase):
     """ FP up-conversion (lower to higher bitwidth)
     """
     def __init__(self, in_pspec, out_pspec):
         self.in_pspec = in_pspec
         self.out_pspec = out_pspec
-        self.i = self.ispec()
-        self.o = self.ospec()
+        super().__init__(in_pspec, "upconvert")
 
     def ispec(self):
         return FPADDBaseData(self.in_pspec)
@@ -28,15 +28,6 @@ class FPCVTUpConvertMod(Elaboratable):
     def ospec(self):
         return FPAddStage1Data(self.out_pspec, e_extra=False)
 
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.upconvert = self
-        m.d.comb += self.i.eq(i)
-
-    def process(self, i):
-        return self.o
-
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb