From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 May 2021 17:08:56 +0000 (+0100)
Subject: new fast3 needs to be remapped to fast1 port in "reduced ports" case in core
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c842b7ff840db1cfa32b7f3ed8f58abdd2d5976;p=soc.git

new fast3 needs to be remapped to fast1 port in "reduced ports" case in core
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index b5fbbebe..18d62eba 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -365,6 +365,8 @@ class NonProductionCore(Elaboratable):
                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
                     if 'fast2' in fuspecs:
                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
+                    if 'fast3' in fuspecs:
+                        fuspecs['fast1'].append(fuspecs.pop('fast3'))
 
             # for each named regfile port, connect up all FUs to that port
             for (regname, fspec) in sort_fuspecs(fuspecs):
@@ -491,6 +493,8 @@ class NonProductionCore(Elaboratable):
                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
                     if 'fast2' in fuspecs:
                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
+                    if 'fast3' in fuspecs:
+                        fuspecs['fast1'].append(fuspecs.pop('fast3'))
 
             for (regname, fspec) in sort_fuspecs(fuspecs):
                 self.connect_wrport(m, fu_bitdict, wrpickers,