From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 04:50:24 +0000 (+0100)
Subject: missed a mul
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c84dabe418354bf0eafcdbbb90bb0ddaa0ec00f;p=riscv-isa-sim.git

missed a mul
---

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index ed55545..f04a19b 100644
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,3 +1,3 @@
 require_extension('M');
 require_rv64;
-WRITE_RD(sext32(RS1 * RS2));
+WRITE_RD(sext32(rv_mul(RS1, RS2)));