From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 13:38:02 +0000 (+0200)
Subject: Added SigPool::check(bit)
X-Git-Tag: yosys-0.4~387
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c86d6106c3ff4cd7628b1206281eb6080f8bf51;p=yosys.git

Added SigPool::check(bit)
---

diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 7035db73d..52e4aa0fb 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -93,6 +93,11 @@ struct SigPool
 		return result;
 	}
 
+	bool check(RTLIL::SigBit bit)
+	{
+		return bit.wire != NULL && bits.count(bit);
+	}
+
 	bool check_any(RTLIL::SigSpec sig)
 	{
 		for (auto &bit : sig)
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 76a905b2c..6c20bddbb 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -251,10 +251,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 			for (int i = 0; i < SIZE(sig); i++) {
 				if (sig[i].wire == NULL)
 					continue;
-				if (!used_signals_nodrivers.check_any(sig[i])) {
+				if (!used_signals_nodrivers.check(sig[i])) {
 					if (!unused_bits.empty())
 						unused_bits += " ";
-					unused_bits += stringf("%zd", i);
+					unused_bits += stringf("%d", i);
 				}
 			}
 			if (unused_bits.empty() || wire->port_id != 0)