From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 20:10:35 +0000 (-0700)
Subject: Re-enable partsel.v test
X-Git-Tag: working-ls180~1237^2~227
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c8a839f13bf7bc8368625ab55960dd3f219b0d8;p=yosys.git

Re-enable partsel.v test
---

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index bf48d007d..af003d52e 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -18,6 +18,5 @@ if ! which iverilog > /dev/null ; then
 fi
 
 cp ../simple/*.v .
-rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails
 DOLLAR='?'
 exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'"