From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 Jan 2022 16:39:02 +0000 (+0000)
Subject: add reporting of PC and instruction being executed to verilator
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c9588bd748910250b09f081ec45c244be187a74;p=microwatt.git

add reporting of PC and instruction being executed to verilator
---

diff --git a/Makefile b/Makefile
index 5bd396d..9fc51ca 100644
--- a/Makefile
+++ b/Makefile
@@ -232,7 +232,7 @@ microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uar
 	    -Wno-COMBDLY  \
 	    -Wno-CASEINCOMPLETE \
 	    -Wno-WIDTH \
-	# --trace
+	# --trace \
 	#    --unroll-count 256 \
 	#    --output-split 5000 \
 	#    --output-split-cfuncs 500 \
diff --git a/core.vhdl b/core.vhdl
index 41b7b45..b33086b 100644
--- a/core.vhdl
+++ b/core.vhdl
@@ -40,7 +40,12 @@ entity core is
 
 	ext_irq		: in std_ulogic;
 
-	terminated_out   : out std_logic
+	terminated_out   : out std_logic;
+
+    -- for verilator debugging
+    nia_req: out std_ulogic;
+    nia: out std_ulogic_vector(63 downto 0);
+    insn: out std_ulogic_vector(31 downto 0)
         );
 end core;
 
@@ -435,7 +440,13 @@ begin
     log_data(150) <= '0';
     log_data(139 downto 135) <= "00000";
 
+    -- snoop and report instruction being executed
+    nia <= icache_to_decode1.nia;
+    insn <= icache_to_decode1.insn;
+    nia_req <= icache_to_decode1.valid and fetch1_to_icache.sequential;
+
     debug_0: entity work.core_debug
+
         generic map (
             LOG_LENGTH => LOG_LENGTH
             )
diff --git a/core_dummy.vhdl b/core_dummy.vhdl
index ae5d49b..9ceab19 100644
--- a/core_dummy.vhdl
+++ b/core_dummy.vhdl
@@ -40,7 +40,12 @@ entity core is
 
 	ext_irq		: in std_ulogic;
 
-	terminated_out   : out std_logic
+	terminated_out   : out std_logic;
+
+    -- for verilator debugging
+    nia_req: out std_ulogic;
+    nia: out std_ulogic_vector(63 downto 0);
+    insn: out std_ulogic_vector(31 downto 0)
         );
 end core;
 
diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 6c23dd7..4524a36 100644
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -36,7 +36,13 @@ entity toplevel is
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
     bram_di   : out std_logic_vector(63 downto 0);
     bram_do   : in std_logic_vector(63 downto 0);
-    bram_sel  : out std_logic_vector(7 downto 0)
+    bram_sel  : out std_logic_vector(7 downto 0);
+
+    -- for verilator debugging
+    nia_req: out std_ulogic;
+    nia: out std_ulogic_vector(63 downto 0);
+    insn: out std_ulogic_vector(31 downto 0)
+
 	);
 end entity toplevel;
 
@@ -104,7 +110,10 @@ begin
         bram_addr           => bram_addr,
         bram_di             => bram_di,
         bram_do             => bram_do,
-        bram_sel            => bram_sel
+        bram_sel            => bram_sel,
+        nia_req           => nia_req,
+        nia               => nia,
+        insn              => insn
 	    );
 
 end architecture behaviour;
diff --git a/soc.vhdl b/soc.vhdl
index 9ab2bab..8440f54 100644
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -117,7 +117,12 @@ entity soc is
         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
 
 	-- DRAM controller signals
-	alt_reset    : in std_ulogic := '0'
+	alt_reset    : in std_ulogic := '0';
+
+    -- for verilator debugging
+    nia_req: out std_ulogic;
+    nia: out std_ulogic_vector(63 downto 0);
+    insn: out std_ulogic_vector(31 downto 0)
 	);
 end entity soc;
 
@@ -267,7 +272,11 @@ architecture behaviour of soc is
         dmi_wr      : in std_ulogic;
         dmi_ack         : out std_ulogic;
         ext_irq     : in std_ulogic;
-        terminated_out   : out std_logic
+        terminated_out   : out std_logic;
+        -- for verilator debugging
+        nia_req: out std_ulogic;
+        nia: out std_ulogic_vector(63 downto 0);
+        insn: out std_ulogic_vector(31 downto 0)
         );
     end component;
 begin
@@ -313,7 +322,10 @@ begin
 	    dmi_wr => dmi_wr,
 	    dmi_ack => dmi_core_ack,
 	    dmi_req => dmi_core_req,
-	    ext_irq => core_ext_irq
+	    ext_irq => core_ext_irq,
+        nia_req           => nia_req,
+        nia               => nia,
+        insn              => insn
 	    );
     end generate;
 
@@ -333,10 +345,14 @@ begin
 	    dmi_wr => dmi_wr,
 	    dmi_ack => dmi_core_ack,
 	    dmi_req => dmi_core_req,
-	    ext_irq => core_ext_irq
+	    ext_irq => core_ext_irq,
+        nia_req           => nia_req,
+        nia               => nia,
+        insn              => insn
 	    );
     end generate;
 
+
     -- Wishbone bus master arbiter & mux
     wb_masters_out <= (0 => wishbone_dcore_out,
 		       1 => wishbone_icore_out,
diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp
index 93abe8a..a409c6e 100644
--- a/verilator/microwatt-verilator.cpp
+++ b/verilator/microwatt-verilator.cpp
@@ -196,15 +196,20 @@ int main(int argc, char **argv)
 		top->uart0_rxd = uart_rx();
 
 #ifdef BRAM_DEBUG
+        if (top->nia_req) {
+            fprintf(dump, "pc %8x insn %8x\n", top->nia, top->insn);
+        }
         if (top->bram_we) {
-            fprintf(dump, "bram wr addr %08x dout %16lx sel %x ",
+            fprintf(dump, "                          " \
+                          "wr @ %08x do %16lx sel %02x ",
                     top->bram_addr, top->bram_di, top->bram_sel);
             ascii_dump((unsigned char*)&top->bram_di, 8, dump);
             fflush(dump);
         }
         // read on one clock delay
         if (top->bram_re) {
-            fprintf(dump, "bram rd addr %08x din %16lx sel %x ",
+            fprintf(dump, "                          " \
+                          "rd @ %08x di %16lx sel %02x ",
                     top->bram_addr, bram_do, top->bram_sel);
             ascii_dump((unsigned char*)&bram_do, 8, dump);
             fflush(dump);