From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 May 2020 03:09:51 +0000 (+0100)
Subject: make 3rd reg for isel NONE however set CRin to BC
X-Git-Tag: convert-csv-opcode-to-binary~2607
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0c9bf739054368f258af9c589b31e6362fdb5d99;p=libreriscv.git

make 3rd reg for isel NONE however set CRin to BC
---

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 47fc68771..39e481b35 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -51,7 +51,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1101111011,,,,,,,,,,,,,,,,,,,,,,,extswsli,XS
 0b1111010110,ALU,OP_ICBI,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,icbi,X
 0b0000010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,icbt,X
------01111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
+-----01111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,NONE,BC,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
 0b0000110100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,1,0,0,NONE,0,1,lbarx,X
 0b0001110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzux,X
 0b0001010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbzx,X