From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 22:10:01 +0000 (-0700)
Subject: Deprecate `abc_scc_break` attribute
X-Git-Tag: working-ls180~881^2^2~224
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ca397f087287307d13daac57f60c24c6f2a982e;p=yosys.git

Deprecate `abc_scc_break` attribute
---

diff --git a/README.md b/README.md
index 56f428548..fe30348eb 100644
--- a/README.md
+++ b/README.md
@@ -409,14 +409,6 @@ Verilog Attributes and non-standard features
   blackbox or whitebox definition to a corresponding entry in a `abc9`
   box-file.
 
-- The port attribute ``abc_scc_break`` indicates a module input port that will
-  be treated as a primary output during `abc9` techmapping. Doing so eliminates
-  the possibility of a strongly-connected component (i.e. a combinatorial loop)
-  existing. Typically, this is specified for sequential inputs on otherwise
-  combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D`
-  port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
-  as a combinatorial loop.
-
 - The port attribute ``abc_carry`` marks the carry-in (if an input port) and
   carry-out (if output port) ports of a box. This information is necessary for
   `abc9` to preserve the integrity of carry-chains. Specifying this attribute