From: Wesley W. Terpstra <wesley@sifive.com>
Date: Fri, 2 Jun 2017 22:56:18 +0000 (-0700)
Subject: vc707axi: track rocketchip API changes (#16)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ca609d324424dc2488e51273ec89c5714d3c95e;p=sifive-blocks.git

vc707axi: track rocketchip API changes (#16)
---

diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index fa4b31b..ac9745f 100644
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -181,7 +181,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
         "device_type"        -> Seq(ResourceString("pci")),
         "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
         "interrupt-map"      -> Seq(1, 2, 3, 4).flatMap(ofMap),
-        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) =>
+        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _, _)) =>
                                                                ResourceMapping(address, BigInt(0x02000000) << 64) },
         "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
           "interrupt-controller" -> Nil,
@@ -211,6 +211,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
 
   val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
     masters = Seq(AXI4MasterParameters(
+      name    = "VC707 PCIe",
       id      = IdRange(0, 1),
       aligned = false)))))