From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Sat, 2 May 2020 05:28:25 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ca93ddd677f1741c63f4d45d4501d36867849ae;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
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+Date: Sat, 02 May 2020 05:28:25 +0000
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+X-Bugzilla-Product: Libre-SOC's first SoC
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-186-13-kKQIsMJROE@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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