From: lkcl <lkcl@web>
Date: Fri, 5 May 2023 21:13:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ca9d0d8af074a1359dbdbe4050527080b2f4cf6;p=libreriscv.git

---

diff --git a/openpower/sv/svstep.mdwn b/openpower/sv/svstep.mdwn
index fb313dbcf..87a3c6b48 100644
--- a/openpower/sv/svstep.mdwn
+++ b/openpower/sv/svstep.mdwn
@@ -132,6 +132,18 @@ is perfectly possible, as is calling of functions, however SVSTATE
 be stored on the stack in order to achieve this benefit not normally
 found in Vector ISAs.
 
+**Use of svstep with sub-vectors**
+
+Incrementing and iteration through subvector state ssubstep and dsubstep is
+possible with `sv.svstep/vecN` where N may be 2/3/4.  However it is necessary
+to use the exact same Sub-Vector qualifier on any Prefixed
+instructions, within any given Vertical-First loop. Also valid
+is not specifying a Sub-vector 
+qualifier at all, but it is critically important to note that
+operations will be repeated.  For example if  `sv.svstep/vec2`
+is used on `sv.addi` then each Vector element operation is
+repeated twice.
+
 -------------
 
 \newpage{}