From: Stephen Twigg <sdtwigg@eecs.berkeley.edu>
Date: Sun, 22 Sep 2013 09:21:13 +0000 (-0700)
Subject: Adjust rocc_inst_t to properly extract fields due to the new ISA encoding.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0cada7f60d7897e6afb2d63fd00cf2e7703967b8;p=riscv-isa-sim.git

Adjust rocc_inst_t to properly extract fields due to the new ISA encoding.
---

diff --git a/riscv/rocc.h b/riscv/rocc.h
index 6deccf8..13980bb 100644
--- a/riscv/rocc.h
+++ b/riscv/rocc.h
@@ -6,13 +6,13 @@
 struct rocc_insn_t
 {
   unsigned opcode : 7;
+  unsigned rd : 5;
   unsigned xs2 : 1;
   unsigned xs1 : 1;
   unsigned xd : 1;
-  unsigned funct : 7;
-  unsigned rs2 : 5;
   unsigned rs1 : 5;
-  unsigned rd : 5;
+  unsigned rs2 : 5;
+  unsigned funct : 7;
 };
 
 class rocc_t : public extension_t