From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Fri, 27 Jul 2007 19:46:45 +0000 (-0700)
Subject: cache/memtest: fixes for functional accesses.
X-Git-Tag: m5_2.0_beta4~195^2~26
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0cbcb715e0f6f2f7b1338d37e641ef931247748f;p=gem5.git

cache/memtest: fixes for functional accesses.

--HG--
extra : convert_revision : 688ba4d882cad2c96cf44c9e46999f74266e02ee
---

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 86a33f44b..83417c514 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -359,7 +359,6 @@ MemTest::tick()
 
         if (probe) {
             cachePort.sendFunctional(pkt);
-            pkt->makeAtomicResponse();
             completeRequest(pkt);
         } else {
             sendPkt(pkt);
@@ -393,7 +392,6 @@ MemTest::tick()
 
         if (probe) {
             cachePort.sendFunctional(pkt);
-            pkt->makeAtomicResponse();
             completeRequest(pkt);
         } else {
             sendPkt(pkt);
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 150cf80b7..c1b01d676 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -641,33 +641,12 @@ Cache<TagStore>::functionalAccess(PacketPtr pkt,
         return;
     }
 
-    // Need to check for outstanding misses and writes
-
-    // There can only be one matching outstanding miss.
-    MSHR *mshr = mshrQueue.findMatch(blk_addr);
-    if (mshr) {
-        MSHR::TargetList *targets = mshr->getTargetList();
-        MSHR::TargetList::iterator i = targets->begin();
-        MSHR::TargetList::iterator end = targets->end();
-        for (; i != end; ++i) {
-            PacketPtr targetPkt = i->pkt;
-            if (pkt->checkFunctional(targetPkt))
-                return;
-        }
+    // Need to check for outstanding misses and writes; if neither one
+    // satisfies, then forward to other side of cache.
+    if (!(mshrQueue.checkFunctional(pkt, blk_addr) ||
+          writeBuffer.checkFunctional(pkt, blk_addr))) {
+        otherSidePort->checkAndSendFunctional(pkt);
     }
-
-    // There can be many matching outstanding writes.
-    std::vector<MSHR*> writes;
-    assert(!writeBuffer.findMatches(blk_addr, writes));
-/*  Need to change this to iterate through targets in mshr??
-    for (int i = 0; i < writes.size(); ++i) {
-        MSHR *mshr = writes[i];
-        if (pkt->checkFunctional(mshr->addr, mshr->size, mshr->writeData))
-            return;
-    }
-*/
-
-    otherSidePort->checkAndSendFunctional(pkt);
 }
 
 
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 5ba3d1ec5..7796773a3 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -118,6 +118,20 @@ MSHR::TargetList::clearDownstreamPending()
 }
 
 
+bool
+MSHR::TargetList::checkFunctional(PacketPtr pkt)
+{
+    Iterator end_i = end();
+    for (Iterator i = begin(); i != end_i; ++i) {
+        if (pkt->checkFunctional(i->pkt)) {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+
 void
 MSHR::allocate(Addr _addr, int _size, PacketPtr target,
                Tick whenReady, Counter _order)
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh
index e850a8633..c865ca3ac 100644
--- a/src/mem/cache/miss/mshr.hh
+++ b/src/mem/cache/miss/mshr.hh
@@ -82,6 +82,7 @@ class MSHR : public Packet::SenderState
         void add(PacketPtr pkt, Tick readyTime, Counter order, bool cpuSide);
         void replaceUpgrades();
         void clearDownstreamPending();
+        bool checkFunctional(PacketPtr pkt);
     };
 
     /** A list of MSHRs. */
@@ -230,6 +231,11 @@ public:
 
     void handleFill(Packet *pkt, CacheBlk *blk);
 
+    bool checkFunctional(PacketPtr pkt) {
+        return (targets->checkFunctional(pkt) ||
+                deferredTargets->checkFunctional(pkt));
+    }
+
     /**
      * Prints the contents of this MSHR to stderr.
      */
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index 50a28fb3c..911329e0c 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -84,9 +84,24 @@ MSHRQueue::findMatches(Addr addr, vector<MSHR*>& matches) const
         }
     }
     return retval;
+}
+
 
+bool
+MSHRQueue::checkFunctional(PacketPtr pkt, Addr blk_addr)
+{
+    MSHR::ConstIterator i = allocatedList.begin();
+    MSHR::ConstIterator end = allocatedList.end();
+    for (; i != end; ++i) {
+        MSHR *mshr = *i;
+        if (mshr->addr == blk_addr && mshr->checkFunctional(pkt)) {
+            return true;
+        }
+    }
+    return false;
 }
 
+
 MSHR *
 MSHRQueue::findPending(Addr addr, int size) const
 {
diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh
index 1f1d59e98..447ebfc5a 100644
--- a/src/mem/cache/miss/mshr_queue.hh
+++ b/src/mem/cache/miss/mshr_queue.hh
@@ -115,6 +115,8 @@ class MSHRQueue
      */
     MSHR *findPending(Addr addr, int size) const;
 
+    bool checkFunctional(PacketPtr pkt, Addr blk_addr);
+
     /**
      * Allocates a new MSHR for the request and size. This places the request
      * as the first target in the MSHR.