From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sat, 23 Apr 2016 02:08:19 +0000 (-0700)
Subject: Fixed typo
X-Git-Tag: yosys-0.7~253
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0cbe70eaa40056a9d41070652282694cd7285b1a;p=yosys.git

Fixed typo
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 40d79aeae..706e955b6 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -235,7 +235,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 	
 	reg[15:0] shreg = 0;
 	
-	always @(posedge clk, negedge RSTN) begin
+	always @(posedge clk, negedge nRST) begin
 		
 		if(!nRST)
 			shreg = 0;